synthesis fixes

rtl/VX_cache/VX_cache_config.v

@@ -27,6 +27,8 @@
 	`define MRVQ_SIZE `REQQ_SIZE
 	// Dram Fill Rsp Queue Size
 	`define DFPQ_SIZE 2
+  // Snoop Req Queue
+  `define SNRQ_SIZE 8
 
 // Queues for writebacks Knobs {1, 2, 4, 8, ...}
 	// Core Writeback Queue Size
@@ -36,6 +38,11 @@
 	// Dram Fill Req Queue Size
 	`define DFQQ_SIZE `REQQ_SIZE
 
+  // Fill Invalidator Active {Comment out define statement to invalidate}
+  `define FILL_INVALIDATOR_ACTIVE 1
+  // Fill Invalidator Size {Fill invalidator must be active}
+  `define FILL_INVALIDAOR_SIZE 16
+
 // Dram knobs
 	`define SIMULATED_DRAM_LATENCY_CYCLES 10