fixed instr/cycle perf counter

2020-11-12 11:41:25 -08:00
parent fceb561cbd
commit 2e0f51af80
8 changed files with 81 additions and 80 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -97,7 +97,7 @@ module VX_bank #(
    input  wire                         snp_rsp_ready,

    // Misses
-    output wire misses
+    output wire                         misses
 );

 `ifdef DBG_CORE_REQ_INFO