diff --git a/rtl/._VX_fetch.v b/rtl/._VX_fetch.v
new file mode 100644
index 00000000..e28521c3
Binary files /dev/null and b/rtl/._VX_fetch.v differ
diff --git a/rtl/._VX_front_end.v b/rtl/._VX_front_end.v
new file mode 100644
index 00000000..e28521c3
Binary files /dev/null and b/rtl/._VX_front_end.v differ
diff --git a/rtl/._VX_generic_register.v b/rtl/._VX_generic_register.v
new file mode 100644
index 00000000..e28521c3
Binary files /dev/null and b/rtl/._VX_generic_register.v differ
diff --git a/rtl/._buses.vh b/rtl/._buses.vh
new file mode 100644
index 00000000..e28521c3
Binary files /dev/null and b/rtl/._buses.vh differ
diff --git a/rtl/VX_f_d_reg.v b/rtl/VX_f_d_reg.v
index e2651ffa..85a42074 100644
--- a/rtl/VX_f_d_reg.v
+++ b/rtl/VX_f_d_reg.v
@@ -1,25 +1,42 @@
+`include "buses.vh"
 
 `include "VX_define.v"
 
 module VX_f_d_reg (
 	  input wire             clk,
 	  input wire             reset,
-	  input wire[31:0]       in_instruction,
 	  input wire             in_valid[`NT_M1:0],
-	  input wire[31:0]       in_curr_PC,
 	  input wire             in_fwd_stall,
 	  input wire             in_freeze,
 	  input wire             in_clone_stall,
-	  input wire[`NW_M1:0]   in_warp_num,
 
 	  output wire[31:0]      out_instruction,
 	  output wire[31:0]      out_curr_PC,
 	  output wire            out_valid[`NT_M1:0],
-	  output wire[`NW_M1:0]  out_warp_num
+	  output wire[`NW_M1:0]  out_warp_num,
+	  /* verilator lint_off UNUSED */
+	  input wire[31:0]       in_instruction,
+	  input wire[31:0]       in_curr_PC,
+	  input wire[`NW_M1:0]   in_warp_num,
+	  input fe_inst_meta_de_t fe_inst_meta_fd
+	  /* verilator lint_on UNUSED */
 );
 
+	// genvar index;
 	// always @(posedge clk) begin
-		// $display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction);
+	// 	// $display("in_instruction: %x\tfe_inst_meta_fd.instruction: %x",in_instruction, fe_inst_meta_fd.instruction);
+	// 	$error("finally");
+	// 	assert (in_instruction == fe_inst_meta_fd.instruction);
+	// 	assert (in_curr_PC     == fe_inst_meta_fd.inst_pc);
+	// 	assert (in_warp_num    == fe_inst_meta_fd.warp_num);
+	// 	for (index = 0; index <= `NT_M1; index = index + 1) assert (in_valid[index] == fe_inst_meta_fd.valid[index]);
+	// end
+
+	// var match;
+	// always @(*) begin
+	// 	match = ;
+	// 	if (!match)
+	// 		$display("in_instruction: %x, fe_inst_meta_fd.instruction: %x",in_instruction ,fe_inst_meta_fd.instruction);
 	// end
 
 	reg[31:0]      instruction;
@@ -29,9 +46,6 @@ module VX_f_d_reg (
 
 	integer reset_cur_thread = 0;
 
-	// always @(in_instruction) begin
-	// 	$display("in_instruction: %h",in_instruction);
-	// end
 
 	always @(posedge clk or posedge reset) begin
 		if(reset) begin
@@ -50,6 +64,11 @@ module VX_f_d_reg (
 			valid       <= in_valid;
 			curr_PC     <= in_curr_PC;
 			warp_num    <= in_warp_num;
+
+			// instruction <= fe_inst_meta_fd.instruction;
+			// valid       <= fe_inst_meta_fd.valid;
+			// curr_PC     <= fe_inst_meta_fd.inst_pc;
+			// warp_num    <= fe_inst_meta_fd.warp_num;
 		end
 	end
 
diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v
index 64f00c27..c9a76133 100644
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -15,7 +15,6 @@ module VX_fetch (
 	input  wire[31:0]     in_jal_dest,
 	input  wire           in_interrupt,
 	input  wire           in_debug,
-	input  wire[31:0]     in_instruction,
 	input  wire           in_thread_mask[`NT_M1:0],
 	input  wire           in_change_mask,
 	input  wire[`NW_M1:0] in_decode_warp_num,
@@ -23,14 +22,17 @@ module VX_fetch (
 	input  wire           in_wspawn,
 	input  wire[31:0]     in_wspawn_pc,
 	input  wire           in_ebreak,
+	input  icache_response_t icache_response,
 
+	output icache_request_t icache_request,
 	output wire[31:0]     out_instruction,
 	output wire           out_delay,
 	output wire[`NW_M1:0] out_warp_num,
 	output wire[31:0]     out_curr_PC,
 	output wire           out_valid[`NT_M1:0],
 	output wire           out_ebreak,
-	output wire[`NW_M1:0] out_which_wspawn
+	output wire[`NW_M1:0] out_which_wspawn,
+	output fe_inst_meta_de_t fe_inst_meta_fd
 );
 
 		reg       stall;
@@ -95,34 +97,34 @@ module VX_fetch (
 
 		`ifdef ONLY
 
-			wire       warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
-			wire       warp_zero_jal         = in_jal         && (in_memory_warp_num == 0);
-			wire       warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == 0);
-			wire       warp_zero_stall       = stall          || (warp_num != 0);
-			wire       warp_zero_wspawn      = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
-			wire[31:0] warp_zero_wspawn_pc   = in_wspawn_pc;
-			wire       warp_zero_remove      = remove_warp && (in_decode_warp_num == 0);
+			// wire       warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
+			// wire       warp_zero_jal         = in_jal         && (in_memory_warp_num == 0);
+			// wire       warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == 0);
+			// wire       warp_zero_stall       = stall          || (warp_num != 0);
+			// wire       warp_zero_wspawn      = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
+			// wire[31:0] warp_zero_wspawn_pc   = in_wspawn_pc;
+			// wire       warp_zero_remove      = remove_warp && (in_decode_warp_num == 0);
 
-			// always @(*) begin : proc_
-			// 	if (warp_zero_remove) $display("4Removing warp: %h", 0);
-			// end
+			// // always @(*) begin : proc_
+			// // 	if (warp_zero_remove) $display("4Removing warp: %h", 0);
+			// // end
 
-			VX_warp VX_Warp(
-				.clk           (clk),
-				.reset         (reset),
-				.stall         (warp_zero_stall),
-				.remove        (warp_zero_remove),
-				.in_thread_mask(in_thread_mask),
-				.in_change_mask(warp_zero_change_mask),
-				.in_jal        (warp_zero_jal),
-				.in_jal_dest   (in_jal_dest),
-				.in_branch_dir (warp_zero_branch),
-				.in_branch_dest(in_branch_dest),
-				.in_wspawn     (warp_zero_wspawn),
-				.in_wspawn_pc  (warp_zero_wspawn_pc),
-				.out_PC        (out_PC),
-				.out_valid     (out_valid)
-				);
+			// VX_warp VX_Warp(
+			// 	.clk           (clk),
+			// 	.reset         (reset),
+			// 	.stall         (warp_zero_stall),
+			// 	.remove        (warp_zero_remove),
+			// 	.in_thread_mask(in_thread_mask),
+			// 	.in_change_mask(warp_zero_change_mask),
+			// 	.in_jal        (warp_zero_jal),
+			// 	.in_jal_dest   (in_jal_dest),
+			// 	.in_branch_dir (warp_zero_branch),
+			// 	.in_branch_dest(in_branch_dest),
+			// 	.in_wspawn     (warp_zero_wspawn),
+			// 	.in_wspawn_pc  (warp_zero_wspawn_pc),
+			// 	.out_PC        (out_PC),
+			// 	.out_valid     (out_valid)
+			// 	);
 
 		`else 
 
@@ -193,13 +195,21 @@ module VX_fetch (
 		`endif
 
 
-
+		assign icache_request.pc_address = out_PC;
 
 		assign out_curr_PC     = out_PC;
 		assign out_warp_num    = warp_num;
 		assign out_delay       = 0;
 
-		assign out_instruction = stall ? 32'b0 : in_instruction;
+		assign out_instruction = (stall) ? 32'b0 : icache_response.instruction;
+
+		assign fe_inst_meta_fd.warp_num = warp_num;
+
+		genvar index;
+		for (index = 0; index <= `NT_M1; index = index + 1) assign fe_inst_meta_fd.valid[index] = out_valid_var[index];
+
+		assign fe_inst_meta_fd.instruction = (stall) ? 32'b0 : icache_response.instruction;;
+		assign fe_inst_meta_fd.inst_pc     = out_PC;
 
 
 
diff --git a/rtl/VX_fetch_old.v b/rtl/VX_fetch_old.v
new file mode 100644
index 00000000..64f00c27
--- /dev/null
+++ b/rtl/VX_fetch_old.v
@@ -0,0 +1,206 @@
+
+`include "VX_define.v"
+
+module VX_fetch (
+	input  wire           clk,
+	input  wire           reset,
+	input  wire           in_branch_dir,
+	input  wire           in_freeze,
+	input  wire[31:0]     in_branch_dest,
+	input  wire           in_branch_stall,
+	input  wire           in_fwd_stall,
+	input  wire           in_branch_stall_exe,
+	input  wire           in_clone_stall,
+	input  wire           in_jal,
+	input  wire[31:0]     in_jal_dest,
+	input  wire           in_interrupt,
+	input  wire           in_debug,
+	input  wire[31:0]     in_instruction,
+	input  wire           in_thread_mask[`NT_M1:0],
+	input  wire           in_change_mask,
+	input  wire[`NW_M1:0] in_decode_warp_num,
+	input  wire[`NW_M1:0] in_memory_warp_num,
+	input  wire           in_wspawn,
+	input  wire[31:0]     in_wspawn_pc,
+	input  wire           in_ebreak,
+
+	output wire[31:0]     out_instruction,
+	output wire           out_delay,
+	output wire[`NW_M1:0] out_warp_num,
+	output wire[31:0]     out_curr_PC,
+	output wire           out_valid[`NT_M1:0],
+	output wire           out_ebreak,
+	output wire[`NW_M1:0] out_which_wspawn
+);
+
+		reg       stall;
+		reg[31:0] out_PC;
+
+		reg[`NW_M1:0] warp_num;
+		reg[`NW_M1:0] warp_state;
+		reg[`NW_M1:0] warp_count;
+
+		// reg[31:0] num_ecalls;
+
+		initial begin
+			warp_num   = 0;
+			warp_state = 0;
+			// num_ecalls = 0;
+			warp_count = 1;
+		end
+
+
+		// always @(posedge clk) begin
+		// 	if (in_ebreak) begin
+		// 		num_ecalls <= num_ecalls + 1;
+		// 		$display("--------> New num_ecalls = %h", num_ecalls+1);
+		// 	end
+		// end
+
+		wire add_warp    = in_wspawn && !in_ebreak && !in_clone_stall;
+		wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
+
+		always @(posedge clk or posedge reset) begin
+			if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
+				warp_num   <= 0;
+			`ifndef ONLY
+			end else if (!warp_glob_valid[warp_num+1]) begin
+				// $display("Skipping one");
+				warp_num   <= warp_num + 2;
+			`endif
+			end else begin
+				warp_num   <= warp_num + 1;
+			end
+
+			if (add_warp) begin
+				warp_state <= warp_state + 1;
+				warp_count <= warp_count + 1;
+				// $display("Adding a new warp %h", warp_state+1);
+			end else if (remove_warp) begin // No removing, just invalidating
+				warp_count <= warp_count - 1;
+				// $display("Removing a warp %h %h", in_decode_warp_num, warp_count);
+				if (warp_count == 2) begin
+					// $display("&&&&&&&&&&&&& STATE 0");
+					warp_state <= 0;
+				end
+			end
+		end
+
+		assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;
+
+
+		assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
+
+		assign out_which_wspawn = (warp_state+1);
+
+		`ifdef ONLY
+
+			wire       warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
+			wire       warp_zero_jal         = in_jal         && (in_memory_warp_num == 0);
+			wire       warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == 0);
+			wire       warp_zero_stall       = stall          || (warp_num != 0);
+			wire       warp_zero_wspawn      = (0 == 0) ? 0 : (in_wspawn && ((warp_state+1) == 0));
+			wire[31:0] warp_zero_wspawn_pc   = in_wspawn_pc;
+			wire       warp_zero_remove      = remove_warp && (in_decode_warp_num == 0);
+
+			// always @(*) begin : proc_
+			// 	if (warp_zero_remove) $display("4Removing warp: %h", 0);
+			// end
+
+			VX_warp VX_Warp(
+				.clk           (clk),
+				.reset         (reset),
+				.stall         (warp_zero_stall),
+				.remove        (warp_zero_remove),
+				.in_thread_mask(in_thread_mask),
+				.in_change_mask(warp_zero_change_mask),
+				.in_jal        (warp_zero_jal),
+				.in_jal_dest   (in_jal_dest),
+				.in_branch_dir (warp_zero_branch),
+				.in_branch_dest(in_branch_dest),
+				.in_wspawn     (warp_zero_wspawn),
+				.in_wspawn_pc  (warp_zero_wspawn_pc),
+				.out_PC        (out_PC),
+				.out_valid     (out_valid)
+				);
+
+		`else 
+
+			wire[31:0] warp_glob_pc[`NW-1:0];
+			wire       warp_glob_valid[`NW-1:0][`NT_M1:0];
+			genvar cur_warp;
+			generate
+				for (cur_warp = 0; cur_warp < `NW; cur_warp = cur_warp + 1)
+				begin
+					wire       warp_zero_change_mask = in_change_mask && (in_decode_warp_num == cur_warp);
+					wire       warp_zero_jal         = in_jal         && (in_memory_warp_num == cur_warp);
+					wire       warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == cur_warp);
+					wire       warp_zero_stall       = stall          || (warp_num != cur_warp);
+					wire       warp_zero_wspawn      = (cur_warp == 0) ? 0 : (in_wspawn && ((warp_state+1) == cur_warp));
+					wire[31:0] warp_zero_wspawn_pc   = in_wspawn_pc;
+					wire       warp_zero_remove      = remove_warp && (in_decode_warp_num == cur_warp);
+
+					// always @(*) begin : proc_
+					// 	if (warp_zero_remove) $display("4Removing warp: %h", cur_warp);
+					// end
+
+					VX_warp VX_Warp(
+						.clk           (clk),
+						.reset         (reset),
+						.stall         (warp_zero_stall),
+						.remove        (warp_zero_remove),
+						.in_thread_mask(in_thread_mask),
+						.in_change_mask(warp_zero_change_mask),
+						.in_jal        (warp_zero_jal),
+						.in_jal_dest   (in_jal_dest),
+						.in_branch_dir (warp_zero_branch),
+						.in_branch_dest(in_branch_dest),
+						.in_wspawn     (warp_zero_wspawn),
+						.in_wspawn_pc  (warp_zero_wspawn_pc),
+						.out_PC        (warp_glob_pc[cur_warp]),
+						.out_valid     (warp_glob_valid[cur_warp])
+						);
+				end
+			endgenerate
+
+
+			reg[31:0] out_PC_var;
+			reg      out_valid_var[`NT_M1:0];
+
+			always @(*) begin : help
+				integer g;
+				integer h;
+				for (g = 0; g < `NW; g = g + 1)
+				begin
+					if (warp_num == g[`NW_M1:0])
+					begin
+						 out_PC_var    = warp_glob_pc[g][31:0];
+						 for (h = 0; h < `NT; h = h + 1) out_valid_var[h] = warp_glob_valid[g][h];
+					end
+				
+				end
+			end
+
+			assign out_PC    = out_PC_var;
+			assign out_valid = out_valid_var;
+
+			// always @(*) begin
+			// 	if (out_valid[0]) begin
+			// 		$display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
+			// 	end
+			// end
+
+		`endif
+
+
+
+
+		assign out_curr_PC     = out_PC;
+		assign out_warp_num    = warp_num;
+		assign out_delay       = 0;
+
+		assign out_instruction = stall ? 32'b0 : in_instruction;
+
+
+
+endmodule
\ No newline at end of file
diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v
new file mode 100644
index 00000000..62917bd5
--- /dev/null
+++ b/rtl/VX_front_end.v
@@ -0,0 +1,16 @@
+
+module VX_front_end (
+	input clk,    // Clock
+	input reset,
+	input icache_response_t icache_response,
+
+
+	output icache_request_t icache_request,
+	
+);
+
+
+
+
+
+endmodule
\ No newline at end of file
diff --git a/rtl/VX_generic_register.v b/rtl/VX_generic_register.v
new file mode 100644
index 00000000..2eb7d070
--- /dev/null
+++ b/rtl/VX_generic_register.v
@@ -0,0 +1,31 @@
+
+
+module VX_generic_register 
+	#(
+		parameter N = 1
+	)
+	(
+		input          clk,
+		input          reset,
+		input          stall,
+		input          flush,
+		input[N-1:0]   in,
+		output [N-1:0] out
+	);
+
+
+	reg[N-1:0] value;
+
+
+	always @(posedge clk or posedge reset) begin
+		if (reset || flush) begin
+			value <= 0;
+		end else if (~stall) begin
+			value <= in;
+		end
+	end
+
+
+	assign out = value;
+
+endmodule
\ No newline at end of file
diff --git a/rtl/Vortex.v b/rtl/Vortex.v
index ce7bee31..773e530b 100644
--- a/rtl/Vortex.v
+++ b/rtl/Vortex.v
@@ -1,14 +1,16 @@
 
 `include "VX_define.v"
+`include "buses.vh"
 
 module Vortex(
 	input  wire           clk,
 	input  wire           reset,
-	input  wire[31:0]     fe_instruction,
-	// input  wire[31:0]     in_cache_driver_out_data_0,
-	// input  wire[31:0]     in_cache_driver_out_data_1,
+	input  wire[31:0] icache_response_instruction,
+	output wire[31:0]  icache_request_pc_address,
+	// input  wire[31:0]     icache_instruction,
+	// output wire           icache_request_valid,
+	// output wire[31:0]     icache_PC,
 	input  wire[31:0]     in_cache_driver_out_data[`NT_M1:0],
-	output wire[31:0]     curr_PC,
 	output wire[31:0]     out_cache_driver_in_address[`NT_M1:0],
 	output wire[2:0]      out_cache_driver_in_mem_read,
 	output wire[2:0]      out_cache_driver_in_mem_write,
@@ -23,8 +25,6 @@ module Vortex(
 // assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
 
 
-assign curr_PC = fetch_curr_PC;
-
 // From fetch
 wire[31:0]     fetch_instruction;
 wire           fetch_delay;
@@ -201,6 +201,14 @@ assign interrupt    = 1'b0;
 assign total_freeze = fetch_delay || memory_delay;
 assign out_ebreak   = fetch_ebreak;
 
+
+icache_response_t icache_response_fe;
+icache_request_t  icache_request_fe;
+fe_inst_meta_de_t fe_inst_meta_fd;
+
+assign icache_response_fe.instruction = icache_response_instruction;
+assign icache_request_pc_address      = icache_request_fe.pc_address;
+
 VX_fetch vx_fetch(
 		.clk                (clk),
 		.reset              (reset),
@@ -215,7 +223,6 @@ VX_fetch vx_fetch(
 		.in_jal_dest        (e_m_jal_dest),
 		.in_interrupt       (interrupt),
 		.in_debug           (debug),
-		.in_instruction     (fe_instruction),
 		.in_thread_mask     (decode_thread_mask),
 		.in_change_mask     (decode_change_mask),
 		.in_decode_warp_num (decode_warp_num),
@@ -223,14 +230,17 @@ VX_fetch vx_fetch(
 		.in_wspawn          (decode_wspawn),
 		.in_wspawn_pc       (decode_wspawn_pc),
 		.in_ebreak          (decode_ebreak),
+		.icache_response    (icache_response_fe),
 
+		.icache_request     (icache_request_fe),
 		.out_instruction    (fetch_instruction),
 		.out_delay          (fetch_delay),
 		.out_curr_PC        (fetch_curr_PC),
 		.out_warp_num       (fetch_warp_num),
 		.out_valid          (fetch_valid),
 		.out_ebreak         (fetch_ebreak),
-		.out_which_wspawn   (fetch_which_warp)
+		.out_which_wspawn   (fetch_which_warp),
+		.fe_inst_meta_fd    (fe_inst_meta_fd)
 	);
 
 
@@ -247,7 +257,8 @@ VX_f_d_reg vx_f_d_reg(
 		.out_instruction(f_d_instruction),
 		.out_curr_PC    (f_d_curr_PC),
 		.out_valid      (f_d_valid),
-		.out_warp_num   (f_d_warp_num)
+		.out_warp_num   (f_d_warp_num),
+		.fe_inst_meta_fd(fe_inst_meta_fd)
 	);
 
 
diff --git a/rtl/buses.vh b/rtl/buses.vh
new file mode 100644
index 00000000..d5eebe6e
--- /dev/null
+++ b/rtl/buses.vh
@@ -0,0 +1,63 @@
+
+`include "VX_define.v"
+
+`ifndef BUSES
+
+`define BUSES
+
+typedef struct packed
+{
+  // logic       valid;
+  logic[31:0] pc_address;
+} icache_request_t;
+
+typedef struct packed
+{
+	// logic       ready;
+	// logic       stall;
+	logic[31:0] instruction;
+} icache_response_t;
+
+typedef struct packed
+{
+	logic[31:0]       instruction;
+	logic[31:0]       inst_pc;
+	logic[`NW_M1:0]   warp_num;
+	logic[`NT_M1:0]   valid;
+
+} fe_inst_meta_de_t;
+
+
+`endif
+
+
+	// wire flush = 1'b0;
+	// wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall;
+
+
+	// fe_inst_meta_de_t meta_out;
+
+	// VX_generic_register #(.N(72)) f_d_reg 
+	// (
+	// 	.clk  (clk),
+	// 	.reset(reset),
+	// 	.stall(stall),
+	// 	.flush(flush),
+	// 	.in   ({fe_inst_meta_de}),
+	// 	.out  ({meta_out})
+	// );
+
+	// genvar index;
+	// generate
+	// 	for (index = 0; index <= `NT_M1; index = index + 1) assign out_valid[index] =  meta_out.valid[index];
+	// endgenerate
+	// // assign out_valid[`NT_M1:0] = meta_out.valid[`NT_M1:0];
+
+
+	// assign out_instruction     = meta_out.instruction;
+	// assign out_curr_PC         = meta_out.inst_pc;
+	// assign out_warp_num        = meta_out.warp_num;
+
+	// always @(*) begin
+	// 	$display("Inst: %x, PC: %x, Valid: %x, warpNum: %x", fe_inst_meta_de.instruction, fe_inst_meta_de.inst_pc, fe_inst_meta_de.valid, fe_inst_meta_de.warp_num);
+	// end
\ No newline at end of file
diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex
index 17b723b2..b4fbfcbe 100755
Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ
diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp
index d9bec965..7f1f3558 100644
--- a/rtl/obj_dir/VVortex.cpp
+++ b/rtl/obj_dir/VVortex.cpp
@@ -262,7 +262,7 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num = 0U;
-    // INITIAL at VX_fetch.v:45
+    // INITIAL at VX_fetch.v:47
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count = 1U;
@@ -4738,7 +4738,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	[0U];
-    // ALWAYS at VX_fetch.v:170
+    // ALWAYS at VX_fetch.v:172
     if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) {
 	vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var 
 	    = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc
@@ -4871,7 +4871,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data
 	[0U];
-    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var;
+    vlTOPp->icache_request_pc_address = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var;
     vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[3U];
     vlTOPp->Vortex__DOT__execute_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
@@ -6904,7 +6904,7 @@ VL_INLINE_OPT void VVortex::_settle__TOP__3(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[7U][0U] 
 	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid
 	[0U];
-    // ALWAYS at VX_fetch.v:170
+    // ALWAYS at VX_fetch.v:172
     if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) {
 	vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] 
 	    = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid
@@ -11854,7 +11854,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 					   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC
 					   : ((IData)(4U) 
 					      + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC)));
-    // ALWAYS at VX_f_d_reg.v:36
+    // ALWAYS at VX_f_d_reg.v:50
     if (vlTOPp->reset) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U;
     } else {
@@ -11948,7 +11948,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 						   : 
 						  ((IData)(4U) 
 						   + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC))));
-    // ALWAYS at VX_fetch.v:63
+    // ALWAYS at VX_fetch.v:65
     __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = 
 	(0xfU & (((((IData)(vlTOPp->reset) | ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num) 
 					      >= (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))) 
@@ -11973,7 +11973,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 	    }
 	}
     }
-    // ALWAYS at VX_f_d_reg.v:36
+    // ALWAYS at VX_f_d_reg.v:50
     if (vlTOPp->reset) {
 	__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U;
     } else {
@@ -11994,7 +11994,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 		[0U];
 	}
     }
-    // ALWAYS at VX_f_d_reg.v:36
+    // ALWAYS at VX_f_d_reg.v:50
     if (vlTOPp->reset) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num = 0U;
     } else {
@@ -12006,7 +12006,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
     }
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count 
 	= __Vdly__Vortex__DOT__vx_fetch__DOT__warp_count;
-    // ALWAYSPOST at VX_f_d_reg.v:42
+    // ALWAYSPOST at VX_f_d_reg.v:56
     if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U;
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U;
@@ -12132,7 +12132,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
-    // ALWAYS at VX_fetch.v:170
+    // ALWAYS at VX_fetch.v:172
     if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) {
 	vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var 
 	    = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc
@@ -12181,7 +12181,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
-    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var;
+    vlTOPp->icache_request_pc_address = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var;
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[3U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[3U];
@@ -12328,7 +12328,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__9(VVortex__Syms* __restrict vlSymsp)
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__9\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    // ALWAYS at VX_f_d_reg.v:36
+    // ALWAYS at VX_f_d_reg.v:50
     if (vlTOPp->reset) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U;
     } else {
@@ -12336,7 +12336,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__9(VVortex__Syms* __restrict vlSymsp)
 		      | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))))) {
 	    vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)
-		    ? 0U : vlTOPp->fe_instruction);
+		    ? 0U : vlTOPp->icache_response_instruction);
 	}
     }
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = 
@@ -13971,11 +13971,11 @@ void VVortex::_ctor_var_reset() {
     // Body
     clk = VL_RAND_RESET_I(1);
     reset = VL_RAND_RESET_I(1);
-    fe_instruction = VL_RAND_RESET_I(32);
+    icache_response_instruction = VL_RAND_RESET_I(32);
+    icache_request_pc_address = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
 	    in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    curr_PC = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
 	    out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
     }}
diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h
index 04c0976e..e26cf049 100644
--- a/rtl/obj_dir/VVortex.h
+++ b/rtl/obj_dir/VVortex.h
@@ -37,8 +37,8 @@ VL_MODULE(VVortex) {
     VL_OUT8(out_cache_driver_in_mem_read,2,0);
     VL_OUT8(out_cache_driver_in_mem_write,2,0);
     VL_OUT8(out_ebreak,0,0);
-    VL_IN(fe_instruction,31,0);
-    VL_OUT(curr_PC,31,0);
+    VL_IN(icache_response_instruction,31,0);
+    VL_OUT(icache_request_pc_address,31,0);
     VL_IN(in_cache_driver_out_data[4],31,0);
     VL_OUT(out_cache_driver_in_address[4],31,0);
     VL_OUT8(out_cache_driver_in_valid[4],0,0);
diff --git a/rtl/obj_dir/VVortex.mk b/rtl/obj_dir/VVortex.mk
index edc5fcca..b75631b6 100644
--- a/rtl/obj_dir/VVortex.mk
+++ b/rtl/obj_dir/VVortex.mk
@@ -33,6 +33,7 @@ VM_PREFIX = VVortex
 VM_MODPREFIX = VVortex
 # User CFLAGS (from -CFLAGS on Verilator command line)
 VM_USER_CFLAGS = \
+	-std=c++11 \
 
 # User LDLIBS (from -LDFLAGS on Verilator command line)
 VM_USER_LDLIBS = \
diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a
index c247ebd7..e1032345 100644
Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ
diff --git a/rtl/obj_dir/VVortex__ALLcls.cpp b/rtl/obj_dir/VVortex__ALLcls.cpp
index 2b2188ef..049be850 100644
--- a/rtl/obj_dir/VVortex__ALLcls.cpp
+++ b/rtl/obj_dir/VVortex__ALLcls.cpp
@@ -1,4 +1,5 @@
 // DESCRIPTION: Generated by verilator_includer via makefile
 #define VL_INCLUDE_OPT include
 #include "VVortex.cpp"
+#include "VVortex___024unit.cpp"
 #include "VVortex_VX_context_slave.cpp"
diff --git a/rtl/obj_dir/VVortex__ALLcls.d b/rtl/obj_dir/VVortex__ALLcls.d
index 18a9ea10..3fd4ad34 100644
--- a/rtl/obj_dir/VVortex__ALLcls.d
+++ b/rtl/obj_dir/VVortex__ALLcls.d
@@ -1,5 +1,5 @@
 VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  VVortex__Syms.h VVortex_VX_context_slave.h \
-  VVortex_VX_context_slave.cpp
+  VVortex__Syms.h VVortex___024unit.h VVortex_VX_context_slave.h \
+  VVortex___024unit.cpp VVortex_VX_context_slave.cpp
diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
index e06e4275..16a42a02 100644
Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ
diff --git a/rtl/obj_dir/VVortex__ALLsup.d b/rtl/obj_dir/VVortex__ALLsup.d
index 290c1bbe..f6a3d876 100644
--- a/rtl/obj_dir/VVortex__ALLsup.d
+++ b/rtl/obj_dir/VVortex__ALLsup.d
@@ -1,4 +1,4 @@
 VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  VVortex.h VVortex_VX_context_slave.h
+  VVortex.h VVortex___024unit.h VVortex_VX_context_slave.h
diff --git a/rtl/obj_dir/VVortex__ALLsup.o b/rtl/obj_dir/VVortex__ALLsup.o
index d79eef46..fc474bdd 100644
Binary files a/rtl/obj_dir/VVortex__ALLsup.o and b/rtl/obj_dir/VVortex__ALLsup.o differ
diff --git a/rtl/obj_dir/VVortex__Syms.cpp b/rtl/obj_dir/VVortex__Syms.cpp
index cd3f36e7..c48f8ef8 100644
--- a/rtl/obj_dir/VVortex__Syms.cpp
+++ b/rtl/obj_dir/VVortex__Syms.cpp
@@ -3,6 +3,7 @@
 
 #include "VVortex__Syms.h"
 #include "VVortex.h"
+#include "VVortex___024unit.h"
 #include "VVortex_VX_context_slave.h"
 
 // FUNCTIONS
diff --git a/rtl/obj_dir/VVortex__Syms.h b/rtl/obj_dir/VVortex__Syms.h
index 10ad45e9..428d6358 100644
--- a/rtl/obj_dir/VVortex__Syms.h
+++ b/rtl/obj_dir/VVortex__Syms.h
@@ -10,6 +10,7 @@
 
 // INCLUDE MODULE CLASSES
 #include "VVortex.h"
+#include "VVortex___024unit.h"
 #include "VVortex_VX_context_slave.h"
 
 // SYMS CLASS
diff --git a/rtl/obj_dir/VVortex___024unit.cpp b/rtl/obj_dir/VVortex___024unit.cpp
new file mode 100644
index 00000000..78ec65b6
--- /dev/null
+++ b/rtl/obj_dir/VVortex___024unit.cpp
@@ -0,0 +1,34 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See VVortex.h for the primary calling header
+
+#include "VVortex___024unit.h"
+#include "VVortex__Syms.h"
+
+
+//--------------------
+// STATIC VARIABLES
+
+
+//--------------------
+
+VL_CTOR_IMP(VVortex___024unit) {
+    // Reset internal values
+    // Reset structure values
+    _ctor_var_reset();
+}
+
+void VVortex___024unit::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
+    if (0 && first) {}  // Prevent unused
+    this->__VlSymsp = vlSymsp;
+}
+
+VVortex___024unit::~VVortex___024unit() {
+}
+
+//--------------------
+// Internal Methods
+
+void VVortex___024unit::_ctor_var_reset() {
+    VL_DEBUG_IF(VL_DBG_MSGF("+        VVortex___024unit::_ctor_var_reset\n"); );
+}
diff --git a/rtl/obj_dir/VVortex___024unit.h b/rtl/obj_dir/VVortex___024unit.h
new file mode 100644
index 00000000..122640fe
--- /dev/null
+++ b/rtl/obj_dir/VVortex___024unit.h
@@ -0,0 +1,45 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design internal header
+// See VVortex.h for the primary calling header
+
+#ifndef _VVortex___024unit_H_
+#define _VVortex___024unit_H_
+
+#include "verilated.h"
+
+class VVortex__Syms;
+
+//----------
+
+VL_MODULE(VVortex___024unit) {
+  public:
+    
+    // PORTS
+    
+    // LOCAL SIGNALS
+    
+    // LOCAL VARIABLES
+    
+    // INTERNAL VARIABLES
+  private:
+    VVortex__Syms* __VlSymsp;  // Symbol table
+  public:
+    
+    // PARAMETERS
+    
+    // CONSTRUCTORS
+  private:
+    VL_UNCOPYABLE(VVortex___024unit);  ///< Copying not allowed
+  public:
+    VVortex___024unit(const char* name="TOP");
+    ~VVortex___024unit();
+    
+    // API METHODS
+    
+    // INTERNAL METHODS
+    void __Vconfigure(VVortex__Syms* symsp, bool first);
+  private:
+    void _ctor_var_reset();
+} VL_ATTR_ALIGNED(128);
+
+#endif // guard
diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d
index 9727d17d..b55bf511 100644
--- a/rtl/obj_dir/VVortex__ver.d
+++ b/rtl/obj_dir/VVortex__ver.d
@@ -1 +1 @@
-obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v 
+obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex___024unit.cpp obj_dir/VVortex___024unit.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v buses.vh 
diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat
index 10bf5d85..b0a7bfbd 100644
--- a/rtl/obj_dir/VVortex__verFiles.dat
+++ b/rtl/obj_dir/VVortex__verFiles.dat
@@ -1,33 +1,36 @@
 # DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "-Wall -cc Vortex.v --exe test_bench.cpp"
+C "-Wall -cc Vortex.v --exe test_bench.cpp -CFLAGS -std=c++11"
 S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
-S      2785 12891069980  1560309956           0  1560309956           0 "VX_alu.v"
-S      3553 12891069981  1560309956           0  1560309956           0 "VX_context.v"
-S      4995 12891069982  1560309956           0  1560309956           0 "VX_context_slave.v"
-S      1699 12891069983  1560311423           0  1560311423           0 "VX_csr_handler.v"
-S      5512 12891069984  1560309956           0  1560309956           0 "VX_d_e_reg.v"
-S     17808 12891069985  1560309956           0  1560309956           0 "VX_decode.v"
-S      1676 12891069987  1560310232           0  1560310232           0 "VX_define.v"
-S      4267 12891069988  1560309956           0  1560309956           0 "VX_e_m_reg.v"
-S      3692 12891069989  1560309956           0  1560309956           0 "VX_execute.v"
-S      1751 12891069990  1560309956           0  1560309956           0 "VX_f_d_reg.v"
-S      6204 12891069991  1560310568           0  1560310568           0 "VX_fetch.v"
-S      6293 12891069992  1560309956           0  1560309956           0 "VX_forwarding.v"
-S      1866 12891069993  1560309956           0  1560309956           0 "VX_m_w_reg.v"
-S      4352 12891069994  1560310451           0  1560310451           0 "VX_memory.v"
-S      1249 12891069995  1560309956           0  1560309956           0 "VX_register_file.v"
-S      1655 12891069996  1560309956           0  1560309956           0 "VX_register_file_master_slave.v"
-S      1599 12891069997  1560309956           0  1560309956           0 "VX_register_file_slave.v"
-S      1915 12891069999  1560309956           0  1560309956           0 "VX_warp.v"
-S      1568 12891070000  1560309956           0  1560309956           0 "VX_writeback.v"
-S     18828 12891070001  1560309956           0  1560309956           0 "Vortex.v"
-T    937577 12891114882  1560311425           0  1560311425           0 "obj_dir/VVortex.cpp"
-T     33907 12891114881  1560311425           0  1560311425           0 "obj_dir/VVortex.h"
-T      1800 12891114886  1560311425           0  1560311425           0 "obj_dir/VVortex.mk"
-T    597541 12891114884  1560311425           0  1560311425           0 "obj_dir/VVortex_VX_context_slave.cpp"
-T     19362 12891114883  1560311425           0  1560311425           0 "obj_dir/VVortex_VX_context_slave.h"
-T      3668 12891114880  1560311425           0  1560311425           0 "obj_dir/VVortex__Syms.cpp"
-T      1547 12891114879  1560311425           0  1560311425           0 "obj_dir/VVortex__Syms.h"
-T       635 12891114889  1560311425           0  1560311425           0 "obj_dir/VVortex__ver.d"
-T         0        0  1560311425           0  1560311425           0 "obj_dir/VVortex__verFiles.dat"
-T      1187 12891114885  1560311425           0  1560311425           0 "obj_dir/VVortex_classes.mk"
+S      2785  1565236  1567474434           0  1567474434           0 "VX_alu.v"
+S      3553  1565237  1567474434           0  1567474434           0 "VX_context.v"
+S      4995  1565238  1567474434           0  1567474434           0 "VX_context_slave.v"
+S      1699  1565239  1567474434           0  1567474434           0 "VX_csr_handler.v"
+S      5512  1565240  1567474434           0  1567474434           0 "VX_d_e_reg.v"
+S     17808  1565241  1567474434           0  1567474434           0 "VX_decode.v"
+S      1676  1565244  1567474434           0  1567474434           0 "VX_define.v"
+S      4267  1565245  1567474434           0  1567474434           0 "VX_e_m_reg.v"
+S      3692  1565246  1567474434           0  1567474434           0 "VX_execute.v"
+S      2537  1567951  1567541896           0  1567541896           0 "VX_f_d_reg.v"
+S      6742  1567193  1567540852           0  1567540852           0 "VX_fetch.v"
+S      6293  1565249  1567474434           0  1567474434           0 "VX_forwarding.v"
+S      1866  1565250  1567474434           0  1567474434           0 "VX_m_w_reg.v"
+S      4352  1565251  1567474434           0  1567474434           0 "VX_memory.v"
+S      1249  1565252  1567474434           0  1567474434           0 "VX_register_file.v"
+S      1655  1565253  1567474434           0  1567474434           0 "VX_register_file_master_slave.v"
+S      1599  1565254  1567474434           0  1567474434           0 "VX_register_file_slave.v"
+S      1915  1565256  1567474434           0  1567474434           0 "VX_warp.v"
+S      1568  1565257  1567474434           0  1567474434           0 "VX_writeback.v"
+S     19239  1565260  1567539986           0  1567539986           0 "Vortex.v"
+S      1335  1565265  1567540424           0  1567540424           0 "buses.vh"
+T    937657  1568790  1567541908           0  1567541908           0 "obj_dir/VVortex.cpp"
+T     33938  1568786  1567541908           0  1567541908           0 "obj_dir/VVortex.h"
+T      1814  1568896  1567541908           0  1567541908           0 "obj_dir/VVortex.mk"
+T    597541  1568856  1567541908           0  1567541908           0 "obj_dir/VVortex_VX_context_slave.cpp"
+T     19362  1568854  1567541908           0  1567541908           0 "obj_dir/VVortex_VX_context_slave.h"
+T      3699  1568785  1567541908           0  1567541908           0 "obj_dir/VVortex__Syms.cpp"
+T      1578  1568784  1567541908           0  1567541908           0 "obj_dir/VVortex__Syms.h"
+T       754  1568852  1567541908           0  1567541908           0 "obj_dir/VVortex___024unit.cpp"
+T       860  1568851  1567541908           0  1567541908           0 "obj_dir/VVortex___024unit.h"
+T       702  1569200  1567541908           0  1567541908           0 "obj_dir/VVortex__ver.d"
+T         0        0  1567541908           0  1567541908           0 "obj_dir/VVortex__verFiles.dat"
+T      1208  1568895  1567541908           0  1567541908           0 "obj_dir/VVortex_classes.mk"
diff --git a/rtl/obj_dir/VVortex_classes.mk b/rtl/obj_dir/VVortex_classes.mk
index 2fa0955e..0395f715 100644
--- a/rtl/obj_dir/VVortex_classes.mk
+++ b/rtl/obj_dir/VVortex_classes.mk
@@ -16,6 +16,7 @@ VM_TRACE = 0
 # Generated module classes, fast-path, compile with highest optimization
 VM_CLASSES_FAST += \
 	VVortex \
+	VVortex___024unit \
 	VVortex_VX_context_slave \
 
 # Generated module classes, non-fast-path, compile with low/medium optimization
diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
index 7403fb1a..9ebfaef9 100644
Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ
diff --git a/rtl/obj_dir/verilated.o b/rtl/obj_dir/verilated.o
index e5cdef37..b1f8abbd 100644
Binary files a/rtl/obj_dir/verilated.o and b/rtl/obj_dir/verilated.o differ
diff --git a/rtl/test_bench.h b/rtl/test_bench.h
index 22c7314a..3256cf67 100644
--- a/rtl/test_bench.h
+++ b/rtl/test_bench.h
@@ -138,9 +138,9 @@ bool Vortex::ibus_driver()
 
     curr_inst = 0xdeadbeef;
 
-    new_PC                             = vortex->curr_PC;
+    new_PC                             = vortex->icache_request_pc_address;
     ram.getWord(new_PC, &curr_inst);
-    vortex->fe_instruction      = curr_inst;
+    vortex->icache_response_instruction   = curr_inst;
 
     // printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
     // printf("\n");