RTL code refactoring
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@@ -8,8 +8,8 @@ module VX_front_end (
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VX_warp_ctl_if warp_ctl_if,
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VX_gpu_dcache_rsp_if icache_rsp_if,
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VX_gpu_dcache_req_if icache_req_if,
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VX_cache_core_rsp_if icache_rsp_if,
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VX_cache_core_req_if icache_req_if,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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@@ -58,7 +58,7 @@ module VX_front_end (
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wire freeze_fi_reg = total_freeze || icache_stage_delay;
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VX_f_d_reg f_i_reg(
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VX_f_d_reg f_i_reg (
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.clk (clk),
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.reset (reset),
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.freeze (freeze_fi_reg),
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@@ -66,7 +66,7 @@ module VX_front_end (
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.fd_inst_meta_de (fe_inst_meta_fi2)
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);
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VX_icache_stage icache_stage(
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VX_icache_stage icache_stage (
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.clk (clk),
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.reset (reset),
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.total_freeze (total_freeze),
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@@ -79,7 +79,7 @@ module VX_front_end (
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.icache_req_if (icache_req_if)
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);
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VX_i_d_reg i_d_reg(
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VX_i_d_reg i_d_reg (
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.clk (clk),
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.reset (reset),
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.freeze (total_freeze),
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@@ -87,7 +87,7 @@ module VX_front_end (
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.fd_inst_meta_de (fd_inst_meta_de)
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);
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VX_decode decode(
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VX_decode decode (
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.fd_inst_meta_de (fd_inst_meta_de),
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.frE_to_bckE_req_if (frE_to_bckE_req_if),
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.wstall_if (wstall_if),
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@@ -97,7 +97,7 @@ module VX_front_end (
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wire no_br_stall = 0;
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VX_d_e_reg d_e_reg(
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VX_d_e_reg d_e_reg (
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.clk (clk),
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.reset (reset),
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.branch_stall (no_br_stall),
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