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fixed make w + vx_gpr_stage csr schedule

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This commit is contained in:
felsabbagh3
2020-02-18 00:26:44 -08:00
parent be66e51613
commit 28ce40eebf
2 changed files with 5 additions and 5 deletions
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2
rtl/Makefile
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@@ -33,7 +33,7 @@ VERILATOR:
VERILATORnoWarnings: VERILATORnoWarnings:
echo "#define VCD_OFF" > simulate/tb_debug.h echo "#define VCD_OFF" > simulate/tb_debug.h
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB)
compdebug: compdebug:
echo "#define VCD_OUTPUT" > simulate/tb_debug.h echo "#define VCD_OUTPUT" > simulate/tb_debug.h

8
rtl/VX_gpr_stage.v
View File

@@ -167,7 +167,7 @@ module VX_gpr_stage (
assign VX_gpu_inst_req.a_reg_data = real_base_address; assign VX_gpu_inst_req.a_reg_data = real_base_address;
assign VX_gpu_inst_req.rd2 = real_store_data; assign VX_gpu_inst_req.rd2 = real_store_data;
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 53)) csr_reg( VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk), .clk (clk),
.reset(reset), .reset(reset),
.stall(stall_gpr_csr), .stall(stall_gpr_csr),
@@ -209,13 +209,13 @@ module VX_gpr_stage (
.out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 }) .out ({VX_gpu_inst_req.valid , VX_gpu_inst_req.warp_num , VX_gpu_inst_req.is_wspawn , VX_gpu_inst_req.is_tmc , VX_gpu_inst_req.is_split , VX_gpu_inst_req.is_barrier , VX_gpu_inst_req.pc_next , VX_gpu_inst_req.a_reg_data , VX_gpu_inst_req.rd2 })
); );
VX_generic_register #(.N(`NW_M1 + 1 + `NT + 53)) csr_reg( VX_generic_register #(.N(`NW_M1 + 1 + `NT + 58)) csr_reg(
.clk (clk), .clk (clk),
.reset(reset), .reset(reset),
.stall(stall_gpr_csr), .stall(stall_gpr_csr),
.flush(flush_rest), .flush(flush_rest),
.in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}), .in ({VX_csr_req_temp.valid, VX_csr_req_temp.warp_num, VX_csr_req_temp.rd, VX_csr_req_temp.wb, VX_csr_req_temp.alu_op, VX_csr_req_temp.is_csr, VX_csr_req_temp.csr_address, VX_csr_req_temp.csr_immed, VX_csr_req_temp.csr_mask}),
.out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask }) .out ({VX_csr_req.valid , VX_csr_req.warp_num , VX_csr_req.rd , VX_csr_req.wb , VX_csr_req.alu_op , VX_csr_req.is_csr , VX_csr_req.csr_address , VX_csr_req.csr_immed , VX_csr_req.csr_mask })
); );
`endif `endif