wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pipeline optimization

Browse Source
This commit is contained in:
Blaise Tine
2020-07-30 03:06:01 -07:00
parent 60e05ae19a
commit 27e95530ef
20 changed files with 184 additions and 340 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/rtl/libs/VX_cam_buffer.v
View File

@@ -12,7 +12,7 @@ module VX_cam_buffer #(
output wire [ADDRW-1:0] write_addr,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
input wire [RPORTS-1:0] release_slot,
output wire full
);

6
hw/rtl/libs/VX_generic_queue.v
View File

@@ -52,11 +52,7 @@ module VX_generic_queue #(
end else begin // (SIZE > 1)
`ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
`else
reg [DATAW-1:0] data [SIZE-1:0];
`endif
`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
if (0 == BUFFERED) begin

34
hw/rtl/libs/VX_generic_stack.v
View File

@@ -1,34 +0,0 @@
`include "VX_platform.vh"
module VX_generic_stack #(
parameter WIDTH = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
always @(posedge clk) begin
if (reset) begin
ptr <= 0;
end else if (push) begin
stack[ptr] <= q1;
stack[ptr+1] <= q2;
ptr <= ptr + 2;
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
endmodule

2
hw/rtl/libs/VX_index_queue.v
View File

@@ -15,7 +15,7 @@ module VX_index_queue #(
input wire [`LOG2UP(SIZE)-1:0] read_addr,
output wire [DATAW-1:0] read_data
);
reg [DATAW-1:0] data [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
reg [SIZE-1:0] valid;
reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;