wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pipeline refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-07-19 05:03:47 -04:00
parent 9cf8bf6149
commit 25f66e6490
71 changed files with 2242 additions and 2379 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
hw/simulate/Makefile
View File

@@ -1,6 +1,8 @@
SINGLECORE += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
# control RTL debug print states
DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
@@ -12,7 +14,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate
@@ -34,13 +36,13 @@ DBG += -DDBG_CORE_REQ_INFO
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
gen-s:
verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG'
verilator $(VF) -DNDEBUG -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'
gen-sd:
verilator $(VF) -cc Vortex.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG)
verilator $(VF) -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(SINGLECORE)' --trace $(DBG)
gen-st:
verilator $(VF) -DNDEBUG -cc Vortex.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
verilator $(VF) -DNDEBUG -cc Vortex.v $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS)
gen-m:
verilator $(VF) -DNDEBUG -cc Vortex.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'

23
hw/simulate/simulator.cpp
View File

@@ -13,6 +13,9 @@ Simulator::Simulator() {
// force random values for unitialized signals
Verilated::randReset(2);
// Turn off assertion before reset
Verilated::assertOn(false);
ram_ = nullptr;
vortex_ = new VVortex();
@@ -49,6 +52,9 @@ void Simulator::reset() {
vortex_->reset = 0;
dram_rsp_vec_.clear();
// Turn on assertion after reset
Verilated::assertOn(true);
}
void Simulator::step() {
@@ -60,6 +66,7 @@ void Simulator::step() {
this->eval_dram_bus();
this->eval_io_bus();
this->eval_csr_bus();
this->eval_snp_bus();
}
@@ -157,6 +164,15 @@ void Simulator::eval_io_bus() {
vortex_->io_rsp_valid = 0;
}
void Simulator::eval_csr_bus() {
vortex_->csr_io_req_valid = 0;
vortex_->csr_io_req_coreid = 0;
vortex_->csr_io_req_addr = 0;
vortex_->csr_io_req_rw = 0;
vortex_->csr_io_req_data = 0;
vortex_->csr_io_rsp_ready = 1;
}
void Simulator::eval_snp_bus() {
if (snp_req_active_) {
if (vortex_->snp_rsp_valid) {
@@ -241,19 +257,18 @@ bool Simulator::run() {
// check riscv-tests PASSED/FAILED status
#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->writeback->last_data_wb & 0xf;
#else
#if (NUM_CLUSTERS == 1)
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->writeback->last_data_wb & 0xf;
#else
int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->writeback->last_data_wb & 0xf;
#endif
#endif
return (status == 1);
}
void Simulator::load_bin(const char* program_file) {
if (ram_ == nullptr)
return;

1
hw/simulate/simulator.h
View File

@@ -52,6 +52,7 @@ private:
void eval_dram_bus();
void eval_io_bus();
void eval_csr_bus();
void eval_snp_bus();
std::vector<dram_req_t> dram_rsp_vec_;

22
hw/simulate/testbench.cpp
View File

@@ -5,12 +5,12 @@
int main(int argc, char **argv)
{
//#define ALL_TESTS
#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[] = {
"../../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
@@ -67,12 +67,14 @@ int main(int argc, char **argv)
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
bool curr = simulator.run();
bool status = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
passed = passed && status;
if (!passed)
break;
}
std::cerr << DEFAULT << "\n***************************************\n";
@@ -95,12 +97,12 @@ int main(int argc, char **argv)
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test);
bool curr = simulator.run();
bool status = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << test << std::endl;
if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
return !curr;
return !status;
#endif
}