pipeline refactoring

hw/rtl/interfaces/VX_lsu_req_if.v

@@ -1,4 +1,3 @@
-
 `ifndef VX_LSU_REQ_IF
 `define VX_LSU_REQ_IF
 
@@ -10,12 +9,13 @@ interface VX_lsu_req_if ();
     wire [31:0]                     curr_PC;
     wire [`NW_BITS-1:0]             warp_num;
     wire [`NUM_THREADS-1:0][31:0]   store_data;
-    wire [`NUM_THREADS-1:0][31:0]   base_addr;  // A reg data
-    wire [31:0]                     offset;     // itype_immed
-    wire [`BYTE_EN_BITS-1:0]        mem_read; 
-    wire [`BYTE_EN_BITS-1:0]        mem_write;
-    wire [4:0]                      rd; // dest register
-    wire [1:0]                      wb; //
+    wire [`NUM_THREADS-1:0][31:0]   base_addr;
+    wire [31:0]                     offset;   
+    wire                            rw; 
+    wire [`BYTEEN_BITS-1:0]         byteen;
+    wire [`NR_BITS-1:0]             rd; 
+    wire [`WB_BITS-1:0]             wb; 
+    wire                            ready;
 
 endinterface