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pipeline refactoring

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This commit is contained in:
Blaise Tine
2020-07-19 05:03:47 -04:00
parent 9cf8bf6149
commit 25f66e6490
71 changed files with 2242 additions and 2379 deletions
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24
hw/rtl/interfaces/VX_alu_req_if.v Normal file
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@@ -0,0 +1,24 @@
`ifndef VX_ALU_REQ_IF
`define VX_ALU_REQ_IF
`include "VX_define.vh"
interface VX_alu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`ALU_BITS-1:0] alu_op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire ready;
endinterface
`endif

40
hw/rtl/interfaces/VX_backend_req_if.v
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@@ -1,40 +0,0 @@
`ifndef VX_FrE_to_BCKBE_REQ_IF
`define VX_FrE_to_BCKBE_REQ_IF
`include "VX_define.vh"
interface VX_backend_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [11:0] csr_addr;
wire is_csr;
wire csr_immed;
wire [31:0] csr_mask;
wire [4:0] rd;
wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] alu_op;
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [`BYTE_EN_BITS-1:0] mem_read;
wire [`BYTE_EN_BITS-1:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire is_etype;
wire is_jal;
wire jal;
wire [31:0] jal_offset;
wire [31:0] next_PC;
// GPGPU stuff
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
endinterface
`endif

15
hw/rtl/interfaces/VX_branch_rsp_if.v
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@@ -1,15 +0,0 @@
`ifndef VX_BRANCH_RSP_IF
`define VX_BRANCH_RSP_IF
`include "VX_define.vh"
interface VX_branch_rsp_if ();
wire valid;
wire dir;
wire [31:0] dest;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif

10
hw/rtl/interfaces/VX_csr_io_req_if.v
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@@ -5,11 +5,11 @@
interface VX_csr_io_req_if ();
wire valid;
wire rw;
wire [11:0] addr;
wire [31:0] data;
wire ready;
wire valid;
wire [`CSR_ADDR_SIZE-1:0] addr;
wire rw;
wire [31:0] data;
wire ready;
endinterface

21
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -6,17 +6,20 @@
interface VX_csr_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] alu_op;
wire is_csr;
wire [11:0] csr_addr;
wire csr_immed;
wire [31:0] csr_mask;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire is_io;
wire [`CSR_BITS-1:0] csr_op;
wire [`CSR_ADDR_SIZE-1:0] csr_addr;
wire [31:0] csr_mask;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire is_io;
wire ready;
endinterface
`endif

33
hw/rtl/interfaces/VX_decode_if.v Normal file
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@@ -0,0 +1,33 @@
`ifndef VX_DECODE_IF
`define VX_DECODE_IF
`include "VX_define.vh"
interface VX_decode_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] next_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] instr_op;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire use_rs1;
wire use_rs2;
wire [`WB_BITS-1:0] wb;
wire ready;
endinterface
`endif

47
hw/rtl/interfaces/VX_exec_unit_req_if.v
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@@ -1,47 +0,0 @@
`ifndef VX_EXE_UNIT_REQ_IF
`define VX_EXE_UNIT_REQ_IF
`include "VX_define.vh"
interface VX_exec_unit_req_if ();
// Meta
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] next_PC;
// Write Back Info
wire [4:0] rd;
wire [1:0] wb;
// Data and alu op
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
wire [4:0] alu_op;
wire [4:0] rs1;
wire [4:0] rs2;
wire rs2_src;
wire [31:0] itype_immed;
wire [19:0] upper_immed;
// Branch type
wire [2:0] branch_type;
// Jal info
wire is_jal;
wire jal;
wire [31:0] jal_offset;
wire is_etype;
wire wspawn;
// CSR info
wire is_csr;
wire [11:0] csr_addr;
wire csr_immed;
wire [31:0] csr_mask;
endinterface
`endif

33
hw/rtl/interfaces/VX_execute_if.v Normal file
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@@ -0,0 +1,33 @@
`ifndef VX_EXECUTE_IF
`define VX_EXECUTE_IF
`include "VX_define.vh"
interface VX_execute_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] instr_op;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [31:0] next_PC;
wire [`WB_BITS-1:0] wb;
wire alu_ready;
wire br_ready;
wire mul_ready;
wire lsu_ready;
wire csr_ready;
wire gpu_ready;
endinterface
`endif

19
hw/rtl/interfaces/VX_gpr_read_if.v
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@@ -1,19 +0,0 @@
`ifndef VX_GPR_READ_IF
`define VX_GPR_READ_IF
`include "VX_define.vh"
interface VX_gpr_read_if ();
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NW_BITS-1:0] warp_num;
wire is_jal;
wire[31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
endinterface
`endif

23
hw/rtl/interfaces/VX_gpu_inst_req_if.v
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@@ -1,23 +0,0 @@
`ifndef VX_GPGPU_INST_REQ_IF
`define VX_GPGPU_INST_REQ_IF
`include "VX_define.vh"
interface VX_gpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
wire[31:0] next_PC;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [31:0] rd2;
endinterface
`endif

21
hw/rtl/interfaces/VX_gpu_req_if.v Normal file
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@@ -0,0 +1,21 @@
`ifndef VX_GPU_REQ_IF
`define VX_GPU_REQ_IF
`include "VX_define.vh"
interface VX_gpu_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] next_PC;
wire [`GPU_BITS-1:0] gpu_op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [31:0] rs2_data;
wire ready;
endinterface
`endif

8
hw/rtl/interfaces/VX_inst_meta_if.v → hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -1,14 +1,14 @@
`ifndef VX_INST_META_IF
`define VX_INST_META_IF
`ifndef VX_IFETCH_REQ_IF
`define VX_IFETCH_REQ_IF
`include "VX_define.vh"
interface VX_inst_meta_if ();
interface VX_ifetch_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] curr_PC;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] instruction;
wire ready;
endinterface

16
hw/rtl/interfaces/VX_ifetch_rsp_if.v Normal file
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@@ -0,0 +1,16 @@
`ifndef VX_IFETCH_RSP_IF
`define VX_IFETCH_RSP_IF
`include "VX_define.vh"
interface VX_ifetch_rsp_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] curr_PC;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] instr;
wire ready;
endinterface
`endif

15
hw/rtl/interfaces/VX_jal_rsp_if.v
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@@ -1,15 +0,0 @@
`ifndef VX_JAL_RSP_IF
`define VX_JAL_RSP_IF
`include "VX_define.vh"
interface VX_jal_rsp_if ();
wire valid;
wire [31:0] dest;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif

1
hw/rtl/interfaces/VX_join_if.v
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@@ -1,4 +1,3 @@
`ifndef VX_JOIN_IF
`define VX_JOIN_IF

14
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -1,4 +1,3 @@
`ifndef VX_LSU_REQ_IF
`define VX_LSU_REQ_IF
@@ -10,12 +9,13 @@ interface VX_lsu_req_if ();
wire [31:0] curr_PC;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr; // A reg data
wire [31:0] offset; // itype_immed
wire [`BYTE_EN_BITS-1:0] mem_read;
wire [`BYTE_EN_BITS-1:0] mem_write;
wire [4:0] rd; // dest register
wire [1:0] wb; //
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire rw;
wire [`BYTEEN_BITS-1:0] byteen;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire ready;
endinterface

24
hw/rtl/interfaces/VX_mul_req_if.v Normal file
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@@ -0,0 +1,24 @@
`ifndef VX_MUL_REQ_IF
`define VX_MUL_REQ_IF
`include "VX_define.vh"
interface VX_mul_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`MUL_BITS-1:0] mul_op;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire ready;
endinterface
`endif

13
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -1,4 +1,3 @@
`ifndef VX_WARP_CTL_IF
`define VX_WARP_CTL_IF
@@ -7,6 +6,7 @@
interface VX_warp_ctl_if ();
wire [`NW_BITS-1:0] warp_num;
wire change_mask;
wire [`NUM_THREADS-1:0] thread_mask;
@@ -16,16 +16,13 @@ interface VX_warp_ctl_if ();
wire whalt;
// barrier
wire is_barrier;
wire [31:0] barrier_id;
wire [$clog2(`NUM_WARPS):0] num_warps;
wire [`NB_BITS-1:0] barrier_id;
wire [`NW_BITS:0] num_warps;
wire is_split;
wire dont_split;
`IGNORE_WARNINGS_BEGIN
wire [`NW_BITS-1:0] split_warp_num;
`IGNORE_WARNINGS_END
wire do_split;
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;

7
hw/rtl/interfaces/VX_wb_if.v
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@@ -6,12 +6,13 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire [`WB_BITS-1:0] wb;
wire is_io;
wire ready;
endinterface