Adding Altera Stratix 10 support

hw/rtl/fp_cores/altera/arria10/acl_fadd.sv

@@ -0,0 +1,67 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_fadd
+// SystemVerilog created on Sun Dec 27 09:47:20 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_fadd (
+    input wire [31:0] a,
+    input wire [31:0] b,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [31:0] fpAddTest_impl_ax0;
+    wire [31:0] fpAddTest_impl_ay0;
+    wire [31:0] fpAddTest_impl_q0;
+    wire fpAddTest_impl_reset0;
+    wire fpAddTest_impl_fpAddTest_impl_ena0;
+
+
+    // fpAddTest_impl(FPCOLUMN,5)@0
+    // out q0@3
+    assign fpAddTest_impl_ax0 = b;
+    assign fpAddTest_impl_ay0 = a;
+    assign fpAddTest_impl_reset0 = areset;
+    assign fpAddTest_impl_fpAddTest_impl_ena0 = en[0];
+    twentynm_fp_mac #(
+        .operation_mode("sp_add"),
+        .ax_clock("0"),
+        .ay_clock("0"),
+        .adder_input_clock("0"),
+        .output_clock("0")
+    ) fpAddTest_impl_DSP0 (
+        .aclr({ fpAddTest_impl_reset0, fpAddTest_impl_reset0 }),
+        .clk({1'b0,1'b0,clk}),
+        .ena({ 1'b0, 1'b0, fpAddTest_impl_fpAddTest_impl_ena0 }),
+        .ax(fpAddTest_impl_ax0),
+        .ay(fpAddTest_impl_ay0),
+        .resulta(fpAddTest_impl_q0),
+        .accumulate(),
+        .az(),
+        .chainin(),
+        .chainout()
+    );
+
+    // xOut(GPOUT,4)@3
+    assign q = fpAddTest_impl_q0;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC0_uid146_invTables_lutmem.hex

@@ -0,0 +1,514 @@
+:020000040000FA
+:0400000040000004B8
+:040001003FE00FFCD1
+:040002003FC03FC4F8
+:040003003FA08F2D5E
+:040004003F80FE0833
+:040005003F618C25A6
+:040006003F423958E4
+:040007003F2305711D
+:040008003F03F0437F
+:040009003EE4F9A137
+:04000A003EC6215D70
+:04000B003EA7674C59
+:04000C003E88CB401F
+:04000D003E6A4D0FEB
+:04000E003E4BEC8CED
+:04000F003E2DA98C4D
+:040010003E0F83E537
+:040011003DF17B6BD7
+:040012003DD38FF457
+:040013003DB5C157DF
+:040014003D980F6A9A
+:040015003D7A7A03B3
+:040016003D5D00F953
+:040017003D3FA424A1
+:040018003D22635CC6
+:040019003D053E77EC
+:04001A003CE8354F3A
+:04001B003CCB47BCD7
+:04001C003CAE7596EB
+:04001D003C91BEB79D
+:04001E003C7522F813
+:04001F003C58A23275
+:040020003C3C3C40E8
+:040021003C1FF0FC94
+:040022003C03C0409B
+:040023003BE7A9E727
+:040024003BCBADCC59
+:040025003BAFCBCA58
+:040026003B9403BD47
+:040027003B7855814C
+:040028003B5CC0F18C
+:040029003B4145EB27
+:04002A003B25E44A44
+:04002B003B0A9BEC05
+:04002C003AEF6CAD8E
+:04002D003AD4566CFF
+:04002E003AB959057D
+:04002F003A9E74562B
+:040030003A83A83E29
+:040031003A68F49B9A
+:040032003A4E594C9D
+:040033003A33D62F57
+:040034003A196B23E7
+:0400350039FF180770
+:0400360039E4DCBC11
+:0400370039CAB921E8
+:0400380039B0AD1618
+:040039003996B87BC1
+:04003A00397CDB3002
+:04003B0039631516FA
+:04003C003949660FC9
+:04003D00392FCDFA90
+:04003E0039164CBA69
+:04003F0038FCE22F78
+:0400400038E38E3DD6
+:0400410038CA50C4A5
+:0400420038B129A602
+:04004300389818C60B
+:04004400387F1E07DC
+:040045003866394C94
+:04004600384D6A7651
+:040047003834B16A2E
+:04004800381C0E0B47
+:040049003803803CBC
+:04004A0037EB07E1A8
+:04004B0037D2A4DE26
+:04004C0037BA571751
+:04004D0037A21E7147
+:04004E003789FACF25
+:04004F003771EC1702
+:040050003759F22DFD
+:0400510037420CF72F
+:04005200372A3C5AB3
+:040053003712803BA5
+:0400540036FAD88020
+:0400550036E3450E3B
+:0400560036CBC5CB15
+:0400570036B45A9FC2
+:04005800369D036E60
+:040059003685C01F09
+:04005A00366E909AD4
+:04005B00365774C4DC
+:04005C0036406C8539
+:04005D00362977C405
+:04005E003612966858
+:04005F0035FBC8584D
+:0400600035E50D7DF8
+:0400610035CE65BE75
+:0400620035B7D103DA
+:0400630035A14F3440
+:04006400358AE039C0
+:04006500357483FC6F
+:04006600355E3A6366
+:0400670035480358BD
+:040068003531DEC58B
+:04006900351BCC91E6
+:04006A003505CCA6E6
+:04006B0034EFDEEEA2
+:04006C0034DA03522D
+:04006D0034C439BBA3
+:04006E0034AE821317
+:04006F003498DC44A1
+:040070003483483855
+:04007100346DC5DA4B
+:040072003458551396
+:040073003442F5CF4F
+:04007400342DA7F789
+:0400750034186B765A
+:0400760034034038D7
+:0400770033EE262717
+:0400780033D91D2E2D
+:0400790033C425392E
+:04007A0033AF3E332F
+:04007B00339A680745
+:04007C003385A2A284
+:04007D003370EDEE01
+:04007E00335C49D9CD
+:04007F003347B64D00
+:0400800033333337AC
+:04008100331EC084E6
+:04008200330A5E1FC0
+:0400830032F60BF650
+:0400840032E1C9F4A8
+:0400850032CD9807D9
+:0400860032B9761CF9
+:0400870032A5641F1B
+:04008800329161FE52
+:04008900327D6FA5B0
+:04008A0032698D0347
+:04008B003255BA052B
+:04008C003241F6986F
+:04008D00322E42A924
+:04008E00321A9E285C
+:04008F00320709012A
+:0400900031F38323A2
+:0400910031E00C7CD2
+:0400920031CCA4FACF
+:0400930031B94C8BA8
+:0400940031A6031E70
+:040095003192C8A23A
+:04009600317F9D0514
+:04009700316C803513
+:040098003159722345
+:04009900314672BCBE
+:04009A00313381F08D
+:04009B0031209FAEC3
+:04009C00310DCBE572
+:04009D0030FB0685A9
+:04009E0030E84F7D7A
+:04009F0030D5A6BDF5
+:0400A00030C30C3528
+:0400A10030B07FD329
+:0400A200309E018902
+:0400A300308B9146C7
+:0400A40030792EF988
+:0400A5003066DA9453
+:0400A6003054940737
+:0400A70030425B4147
+:0400A8003030303490
+:0400A900301E12D023
+:0400AA00300C03050E
+:0400AB002FFA00C464
+:0400AC002FE80BFE30
+:0400AD002FD624A482
+:0400AE002FC44AA76A
+:0400AF002FB27DF7F8
+:0400B0002FA0BE8738
+:0400B1002F8F0C473A
+:0400B2002F7D67280F
+:0400B3002F6BCF1DC3
+:0400B4002F5A441665
+:0400B5002F48C60505
+:0400B6002F3754DBB1
+:0400B7002F25F08B76
+:0400B8002F14990761
+:0400B9002F034E3F84
+:0400BA002EF21027EB
+:0400BB002EE0DEB0A5
+:0400BC002ECFB9CCBE
+:0400BD002EBEA16E44
+:0400BE002EAD958846
+:0400BF002E9C960CD1
+:0400C0002E8BA2EDF4
+:0400C1002E7ABC1DBA
+:0400C2002E69E18E34
+:0400C3002E5913356A
+:0400C4002E4851026F
+:0400C5002E379AEA4E
+:0400C6002E26F0DF13
+:0400C7002E1652D4CB
+:0400C8002E05C0BC85
+:0400C9002DF53A8A4D
+:0400CA002DE4C0322F
+:0400CB002DD451A639
+:0400CC002DC3EEDA78
+:0400CD002DB397C2F6
+:0400CE002DA34C51C1
+:0400CF002D930C7AE7
+:0400D0002D82D83174
+:0400D1002D72AF6B72
+:0400D2002D629219F0
+:0400D3002D528031F9
+:0400D4002D4279A799
+:0400D5002D327E6DDD
+:0400D6002D228E79D0
+:0400D7002D12A9BE7F
+:0400D8002D02D031F4
+:0400D9002CF301C53E
+:0400DA002CE33E7065
+:0400DB002CD3862577
+:0400DC002CC3D8D980
+:0400DD002CB4368089
+:0400DE002CA49F0EA1
+:0400DF002C95127AD0
+:0400E0002C8590B625
+:0400E1002C7619B8A8
+:0400E2002C66AD7566
+:0400E3002C574BE16A
+:0400E4002C47F4F2BF
+:0400E5002C38A89C6F
+:0400E6002C2966D487
+:0400E7002C1A2F9010
+:0400E8002C0B02C516
+:0400E9002BFBE067A6
+:0400EA002BECC86CC7
+:0400EB002BDDBACA85
+:0400EC002BCEB776EA
+:0400ED002BBFBE6403
+:0400EE002BB0CF8CD8
+:0400EF002BA1EAE275
+:0400F0002B93105BE3
+:0400F1002B843FEE2F
+:0400F2002B75799160
+:0400F3002B66BD3883
+:0400F4002B580ADAA1
+:0400F5002B49626DC4
+:0400F6002B3AC3E6F8
+:0400F7002B2C2F3C43
+:0400F8002B1DA465B3
+:0400F9002B0F235650
+:0400FA002B00AC0724
+:0400FB002AF23E6C3B
+:0400FC002AE3DA7D9C
+:0400FD002AD5802F51
+:0400FE002AC72F7965
+:0400FF002AB8E851E2
+:040100002AAAAAAFCE
+:040101002A9C768737
+:040102002A8E4BD125
+:040103002A802A84A0
+:040104002A721296B3
+:040105002A6403FD68
+:040106002A55FEB1C7
+:040107002A4802A8D8
+:040108002A3A0FDAA6
+:040109002A2C263C3A
+:04010A002A1E45C69E
+:04010B002A106E6FD9
+:04010C002A02A02EF5
+:04010D0029F4DAFAFD
+:04010E0029E71ECAF5
+:04010F0029D96B95EA
+:0401100029CBC152E4
+:0401110029BE1FFAEA
+:0401120029B0878207
+:0401130029A2F7E244
+:0401140029957112A6
+:040115002987F3093A
+:04011600297A7DBF06
+:04011700296D112B12
+:04011800295FAD4569
+:040119002952520312
+:04011A002944FF5F16
+:04011B002937B54F7C
+:04011C00292A73CB4E
+:04011D00291D3ACC92
+:04011E0029100A4852
+:04011F002902E23897
+:0401200028F5C29369
+:0401210028E8AB52CD
+:0401220028DB9C6DCD
+:0401230028CE95DB72
+:0401240028C19794C3
+:0401250028B4A191C8
+:0401260028A7B3CA89
+:04012700289ACE360E
+:04012800288DF0CF5F
+:0401290028811B8C82
+:04012A0028744E6582
+:04012B002867895464
+:04012C00285ACC5031
+:04012D00284E1751F0
+:04012E0028416A51A9
+:04012F002834C54764
+:040130002828282C27
+:04013100281B92F9FC
+:04013200280F05A6E7
+:040133002802802CF2
+:0401340027F6028325
+:0401350027E98CA585
+:0401360027DD1E891A
+:0401370027D0B829EC
+:0401380027C4597E01
+:0401390027B8027F62
+:04013A0027ABB32715
+:04013B00279F6B6E21
+:04013C0027932B4D8D
+:04013D002786F2BD62
+:04013E00277AC1B6A5
+:04013F00276E98335C
+:040140002762762B91
+:0401410027565B9949
+:04014200274A48758B
+:04014300273E3CB85F
+:040144002732385CCA
+:0401450027263B5AD4
+:04014600271A45AB84
+:04014700270E5748E0
+:040148002702702BEF
+:0401490026F6904DB9
+:04014A0026EAB7A842
+:04014B0026DEE63492
+:04014C0026D31BECAF
+:04014D0026C758C8A1
+:04014E0026BB9CC36D
+:04014F0026AFE7D61A
+:0401500026A439FAAE
+:040151002698932A2F
+:04015200268CF35EA6
+:0401530026815A9017
+:040154002675C8BB89
+:04015500266A3DD702
+:04015600265EB9DF89
+:0401570026533CCC23
+:040158002647C698D8
+:04015900263C573EAB
+:04015A002630EEB6A7
+:04015B0026258CFBCE
+:04015C00261A320627
+:04015D00260EDDD3BA
+:04015E002603905A8A
+:04015F0025F84995A1
+:0401600025ED097F01
+:0401610025E1D012B2
+:0401620025D69D48B9
+:0401630025CB711B1C
+:0401640025C04B85E2
+:0401650025B52C8010
+:0401660025AA1406AC
+:04016700259F0213BB
+:040168002593F69F46
+:040169002588F1A64E
+:04016A00257DF321DB
+:04016B002572FB0BF3
+:04016C002568095E9B
+:04016D00255D1E15D9
+:04016E002552392AB3
+:04016F0025475A972F
+:04017000253C825850
+:040171002531B0661E
+:040172002526E4BB9F
+:04017300251C1F54D4
+:0401740025116029C8
+:040175002506A7367E
+:0401760024FBF475FD
+:0401770024F147E147
+:0401780024E6A17563
+:0401790024DC012B56
+:04017A0024D166FE28
+:04017B0024C6D2E8DC
+:04017C0024BC44E576
+:04017D0024B1BCEFFE
+:04017E0024A73B0176
+:04017F00249CBF16E7
+:040180002492492953
+:040181002487D934C2
+:04018200247D6F3237
+:0401830024730B1FB7
+:040184002468ACF54A
+:04018500245E54B0F0
+:0401860024540249B2
+:040187002449B5BD95
+:04018800243F6F069B
+:0401890024352E20CB
+:04018A00242AF3052B
+:04018B002420BDB0BF
+:04018C0024168E1D8A
+:04018D00240C644694
+:04018E0024024028DF
+:04018F0023F821BD73
+:0401900023EE08FF53
+:0401910023E3F5EC83
+:0401920023D9E87D08
+:0401930023CFE0AEE8
+:0401940023C5DE7A27
+:0401950023BBE1DDCA
+:0401960023B1EAD2D5
+:0401970023A7F9544D
+:04019800239E0D5F36
+:04019900239426EE97
+:04019A00238A45FC73
+:04019B0023806A85CE
+:04019C0023769485AD
+:04019D00236CC3F616
+:04019E002362F8D40C
+:04019F002359331B92
+:0401A000234F72C6B1
+:0401A1002345B7D16A
+:0401A200233C0238C0
+:0401A300233251F5BD
+:0401A4002328A70560
+:0401A500231F0163B0
+:0401A6002315610BB1
+:0401A700230BC5F869
+:0401A80023023027D7
+:0401A90022F89F9207
+:0401AA0022EF1436F6
+:0401AB0022E58E0EAD
+:0401AC0022DC0D162E
+:0401AD0022D2914A7F
+:0401AE0022C91AA6A2
+:0401AF0022BFA9259D
+:0401B00022B63CC374
+:0401B10022ACD57C2B
+:0401B20022A3734CC5
+:0401B300229A162F47
+:0401B4002290BE20B7
+:0401B50022876B1C16
+:0401B600227E1D1E6A
+:0401B7002274D423B7
+:0401B800226B902600
+:0401B9002262512449
+:0401BA002259171897
+:0401BB00224FE1FEF0
+:0401BC002246B1D353
+:0401BD00223D8692C7
+:0401BE002234603750
+:0401BF00222B3EBFF2
+:0401C00022222226AF
+:0401C10022190A688D
+:0401C200220FF78091
+:0401C3002206E96BBC
+:0401C40021FDE02613
+:0401C50021F4DBAC9A
+:0401C60021EBDBF955
+:0401C70021E2E10B45
+:0401C80021D9EADC73
+:0401C90021D0F969DF
+:0401CA0021C80CAF8D
+:0401CB0021BF24AA82
+:0401CC0021B64155C2
+:0401CD0021AD62AE50
+:0401CE0021A488B030
+:0401CF00219BB35964
+:0401D0002192E2A3F3
+:0401D100218A168DDC
+:0401D20021814F1127
+:0401D30021788C2DD6
+:0401D400216FCDDCEE
+:0401D5002167141C6E
+:0401D600215E5EE860
+:0401D7002155AE3EC2
+:0401D800214D02199A
+:0401D90021445A76ED
+:0401DA00213BB751BD
+:0401DB00213318A80C
+:0401DC00212A7E76E0
+:0401DD002121E8B83C
+:0401DE002119576B21
+:0401DF002110CA8B96
+:0401E000210842149C
+:0401E10020FFBE0439
+:0401E20020F73E576D
+:0401E30020EEC30A3D
+:0401E40020E64C19AC
+:0401E50020DDD980C0
+:0401E60020D56B3D78
+:0401E70020CD014CDA
+:0401E80020C49BAAEA
+:0401E90020BC3A53A9
+:0401EA0020B3DD451C
+:0401EB0020AB847B46
+:0401EC0020A32FF429
+:0401ED00209ADFAACB
+:0401EE002092939C2C
+:0401EF00208A4BC651
+:0401F000208208243D
+:0401F1002079C8B5F4
+:0401F20020718D7378
+:0401F3002069565DCC
+:0401F4002061236EF5
+:0401F5002058F4A5F5
+:0401F6002050C9FDCF
+:0401F7002048A37485
+:0401F800204081061C
+:0401F900203862B197
+:0401FA0020304871F8
+:0401FB002028324343
+:0401FC00202020247B
+:0401FD0020181212A2
+:0401FE0020100808BD
+:0401FF0020080204CE
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC1_uid149_invTables_lutmem.hex

@@ -0,0 +1,514 @@
+:020000040000FA
+:03000000200004D9
+:03000100201FEBD2
+:03000200203FA4F8
+:03000300205F2E4D
+:03000400207E87D4
+:03000500209DB685
+:0300060020BCB16A
+:0300070020DB817A
+:0300080020FA23B8
+:0300090021189625
+:03000A002136E2BA
+:03000B002154FC81
+:03000C002172EF6F
+:03000D002190B08F
+:03000E0021AE4AD6
+:03000F0021CBB949
+:0300100021E8FAEA
+:03001100220612B2
+:03001200222302A4
+:03001300223FC7C2
+:03001400225C600B
+:030015002278D17D
+:0300160022951C14
+:0300170022B13DD6
+:0300180022CD32C4
+:0300190022E905D4
+:03001A002304AC10
+:03001B0023202C73
+:03001C00233B87FC
+:03001D002356BAAD
+:03001E002371C784
+:03001F00238CAF80
+:0300200023A76FA4
+:0300210023C209EE
+:0300220023DC7F5D
+:0300230023F6CFF2
+:030024002410FBAA
+:03002500242B0386
+:030026002444E58A
+:03002700245EA2B2
+:03002800247840F9
+:030029002491B669
+:03002A0024AB0AFA
+:03002B0024C439B1
+:03002C0024DD4A86
+:03002D0024F63482
+:03002E00250EFD9F
+:03002F002527A6DC
+:0300300025402C3C
+:03003100255891BE
+:030032002570D165
+:030033002588F22B
+:0300340025A0F311
+:0300350025B8D615
+:0300360025D0973B
+:0300370025E83683
+:0300380025FFB4ED
+:0300390026171473
+:03003A00262E551A
+:03003B00264578DF
+:03003C00265C79C6
+:03003D0026735EC9
+:03003E00268A22ED
+:03003F0026A0CB2D
+:0300400026B7518F
+:0300410026CDBB0E
+:0300420026E408A9
+:0300430026FA3961
+:0300440027104C36
+:0300450027263D2E
+:03004600273C183C
+:030047002751D36B
+:03004800276770B7
+:03004900277CF21F
+:03004A00279258A2
+:03004B0027A7A242
+:03004C0027BCD0FE
+:03004D0027D1E2D6
+:03004E0027E6DAC8
+:03004F0027FBB5D7
+:03005000281078FD
+:0300510028251F40
+:030052002839A9A1
+:03005300284E191B
+:0300540028626FB0
+:030055002876AB5F
+:03005600288AD025
+:03005700289ED60A
+:0300580028B2C605
+:0300590028C69D19
+:03005A0028DA574A
+:03005B0028EDFB92
+:03005C00290185F2
+:03005D002914F66D
+:03005E0029284E00
+:03005F00293B93A7
+:03006000294EBA6C
+:030061002961CA48
+:030062002974C23C
+:030063002987A149
+:03006400299A6B6B
+:0300650029AD19A9
+:0300660029BFB4FB
+:0300670029D23863
+:0300680029E4A2E6
+:0300690029F6F67F
+:03006A002A09362A
+:03006B002A1B5BF2
+:03006C002A2D6AD0
+:03006D002A3F64C3
+:03006E002A514ACA
+:03006F002A6318E9
+:030070002A74D31C
+:030071002A867369
+:030072002A9802C7
+:030073002AA97740
+:030074002ABAD8CD
+:030075002ACC276B
+:030076002ADD5D23
+:030077002AEE80EE
+:030078002AFF8FCD
+:030079002B1087C2
+:03007A002B216CCB
+:03007B002B323DE8
+:03007C002B42F81C
+:03007D002B53A161
+:03007E002B6433BD
+:03007F002B74B42B
+:030080002B8521AC
+:030081002B957844
+:030082002BA5BEED
+:030083002BB5EEAC
+:030084002BC60E7A
+:030085002BD6195E
+:030086002BE61056
+:030087002BF5F561
+:030088002C05C67E
+:030089002C1589AA
+:03008A002C2535ED
+:03008B002C34CD45
+:03008C002C4455AC
+:03008D002C53CE23
+:03008E002C6331AF
+:03008F002C72834D
+:030090002C81C3FD
+:030091002C90F0C0
+:030092002CA00C93
+:030093002CAF1877
+:030094002CBE116E
+:030095002CCCF779
+:030096002CDBCC94
+:030097002CEA95BB
+:030098002CF947F9
+:030099002D07EB45
+:03009A002D167DA3
+:03009B002D24FF12
+:03009C002D33728F
+:03009D002D41D121
+:03009E002D5023BF
+:03009F002D5E6172
+:0300A0002D6C8F35
+:0300A1002D7AAF06
+:0300A2002D88BCEA
+:0300A3002D96BADD
+:0300A4002DA4AEDA
+:0300A5002DB28CED
+:0300A6002DC05A10
+:0300A7002DCE1C3F
+:0300A8002DDBCB82
+:0300A9002DE96BD3
+:0300AA002DF6FD33
+:0300AB002E0480A0
+:0300AC002E11F41E
+:0300AD002E1F57AC
+:0300AE002E2CAD48
+:0300AF002E39F5F2
+:0300B0002E472BAD
+:0300B1002E545575
+:0300B2002E61704C
+:0300B3002E6E7935
+:0300B4002E7B762A
+:0300B5002E88642E
+:0300B6002E95483C
+:0300B7002EA21B5B
+:0300B8002EAEDC8D
+:0300B9002EBB96C5
+:0300BA002EC83D10
+:0300BB002ED4D769
+:0300BC002EE164CE
+:0300BD002EEDE243
+:0300BE002EFA52C5
+:0300BF002F06B554
+:0300C0002F130AF1
+:0300C1002F1F529C
+:0300C2002F2B9150
+:0300C3002F37BC18
+:0300C4002F43E1E6
+:0300C5002F4FF3C7
+:0300C6002F5BF9B4
+:0300C7002F67F2AE
+:0300C8002F73DFB4
+:0300C9002F7FBFC7
+:0300CA002F8B91E8
+:0300CB002F975715
+:0300CC002FA3144B
+:0300CD002FAEC093
+:0300CE002FBA5FE7
+:0300CF002FC5F347
+:0300D0002FD17CB1
+:0300D1002FDCF62B
+:0300D2002FE868AC
+:0300D3002FF3CA3E
+:0300D4002FFF20DB
+:0300D500300A6D81
+:0300D6003015AC36
+:0300D7003020E0F6
+:0300D800302C06C3
+:0300D90030372499
+:0300DA003042337E
+:0300DB00304D366F
+:0300DC0030582E6B
+:0300DD0030631C71
+:0300DE00306E0180
+:0300DF003078D6A0
+:0300E0003083A3C7
+:0300E100308E63FB
+:0300E2003099183A
+:0300E30030A3C384
+:0300E40030AE60DB
+:0300E50030B8F53B
+:0300E60030C37FA5
+:0300E70030CDFB1E
+:0300E80030D86DA0
+:0300E90030E2D72B
+:0300EA0030ED36C0
+:0300EB0030F78764
+:0300EC003101CD12
+:0300ED00310C0FC4
+:0300EE0031164088
+:0300EF0031206954
+:0300F000312A8A28
+:0300F10031349D0A
+:0300F200313EA6F6
+:0300F3003148A7EA
+:0300F40031529DE9
+:0300F500315C89F2
+:0300F60031666C04
+:0300F70031704322
+:0300F800317A104A
+:0300F9003183D47C
+:0300FA00318D8CB9
+:0300FB0031973DFD
+:0300FC0031A0E24E
+:0300FD0031AA80A5
+:0300FE0031B41406
+:0300FF0031BD9E72
+:0301000031C71CE8
+:0301010031D09565
+:0301020031DA03EC
+:0301030031E36580
+:0301040031ECBF1C
+:0301050031F612BE
+:0301060031FF5A6C
+:0301070032089823
+:030108003211CBE6
+:03010900321AF9AE
+:03010A0032241D7F
+:03010B00322D375B
+:03010C0032364741
+:03010D00323F4F2F
+:03010E0032484E26
+:03010F0032514723
+:03011000325A352B
+:030111003263183E
+:03011200326BF657
+:030113003274CC77
+:03011400327D96A3
+:0301150032865BD4
+:03011600328F1411
+:030117003297C557
+:0301180032A06DA5
+:0301190032A910F8
+:03011A0032B1A857
+:03011B0032BA39BC
+:03011C0032C2C22A
+:03011D0032CB40A2
+:03011E0032D3B821
+:03011F0032DC28A7
+:0301200032E49135
+:0301210032ECEFCE
+:0301220032F5446F
+:0301230032FD9416
+:030124003305DDC3
+:03012500330E1C7A
+:030126003316533A
+:03012700331E85FF
+:030128003326ACCF
+:03012900332ECDA5
+:03012A003336E782
+:03012B00333EF66A
+:03012C0033470056
+:03012D00334F034A
+:03012E003356FC49
+:03012F00335EEF4D
+:030130003366DC57
+:03013100336EBF6B
+:0301320033769C85
+:03013300337E71A7
+:0301340033863FD0
+:03013500338E0501
+:030136003395C638
+:03013700339D7D78
+:0301380033A52BC1
+:0301390033ACD90B
+:03013A0033B47B60
+:03013B0033BC15BD
+:03013C0033C3A822
+:03013D0033CB368B
+:03013E0033D2BEFB
+:03013F0033DA3C74
+:0301400033E1B6F2
+:0301410033E92778
+:0301420033F09205
+:0301430033F7F798
+:0301440033FF5333
+:030145003406A8D5
+:03014600340DF87D
+:030147003415422A
+:03014800341C84E0
+:030149003423BF9D
+:03014A00342AF460
+:03014B0034322328
+:03014C0034394BF8
+:03014D0034406FCC
+:03014E00344789AA
+:03014F00344E9E8D
+:030150003455AC77
+:03015100345CB269
+:030152003463B45F
+:03015300346AB05B
+:030154003471A45F
+:0301550034789368
+:03015600347F7B78
+:0301570034865F8C
+:03015800348D3BA8
+:0301590034940FCC
+:03015A00349ADFF5
+:03015B0034A1AA22
+:03015C0034A86E56
+:03015D0034AF2993
+:03015E0034B5E1D4
+:03015F0034BC9518
+:0301600034C34164
+:0301610034C9E7B7
+:0301620034D08511
+:0301630034D71E70
+:0301640034DDB2D5
+:0301650034E4423D
+:0301660034EACCAC
+:0301670034F14D23
+:0301680034F7CA9F
+:0301690034FE4021
+:03016A003504B2A7
+:03016B00350B1F32
+:03016C00351186C4
+:03016D003517E75C
+:03016E00351E43F8
+:03016F003524999B
+:03017000352AE746
+:03017100353131F4
+:0301720035377AA4
+:03017300353DB760
+:030174003543F31D
+:03017500354A28E0
+:03017600355059A8
+:0301770035568377
+:03017800355CA64D
+:030179003562C527
+:03017A003568DF06
+:03017B00356EF5E9
+:03017C00357505D1
+:03017D00357B10BF
+:03017E00358115B3
+:03017F00358714AD
+:03018000358D0EAC
+:03018100359305AE
+:030182003598F8B5
+:03018300359EE3C3
+:0301840035A4CAD5
+:0301850035AAAAEE
+:0301860035B08908
+:0301870035B66129
+:0301880035BC3350
+:0301890035C1FF7E
+:03018A0035C7C8AE
+:03018B0035CD8DE2
+:03018C0035D34B1D
+:03018D0035D90958
+:03018E0035DEBC9F
+:03018F0035E46BE9
+:0301900035EA1A33
+:0301910035EFC087
+:0301920035F562DE
+:0301930035FAFF3B
+:0301940036009B97
+:0301950036062FFC
+:03019600360BBF66
+:0301970036114AD4
+:030198003616CF49
+:03019900361C50C1
+:03019A003621CE3D
+:03019B00362745BF
+:03019C00362CB747
+:03019D00363227D0
+:03019E003637935E
+:03019F00363CFAF1
+:0301A00036425E86
+:0301A1003647BB23
+:0301A200364D12C5
+:0301A30036526869
+:0301A4003657B912
+:0301A500365D05BF
+:0301A60036624B73
+:0301A70036679127
+:0301A800366CCFE3
+:0301A90036720AA1
+:0301AA0036774065
+:0301AB00367C732C
+:0301AC003681A2F7
+:0301AD003686CAC9
+:0301AE00368BEE9F
+:0301AF0036910F77
+:0301B00036962C54
+:0301B100369B4634
+:0301B20036A05A1A
+:0301B30036A56A04
+:0301B40036AA78F0
+:0301B50036AF81E1
+:0301B60036B486D6
+:0301B70036B987CF
+:0301B80036BE83CD
+:0301B90036C379D1
+:0301BA0036C86ED6
+:0301BB0036CD5EE0
+:0301BC0036D249EF
+:0301BD0036D733FF
+:0301BE0036DC1A12
+:0301BF0036E0FA2D
+:0301C00036E5D54C
+:0301C10036EAAD6E
+:0301C20036EF8491
+:0301C30036F455BA
+:0301C40036F921E8
+:0301C50036FDEB19
+:0301C6003702B14C
+:0301C70037077087
+:0301C800370C30C1
+:0301C9003710EB01
+:0301CA003715A046
+:0301CB00371A538D
+:0301CC00371F04D6
+:0301CD003723AF26
+:0301CE0037285877
+:0301CF00372CF9D1
+:0301D00037319C28
+:0301D10037363787
+:0301D200373AD1E8
+:0301D300373F664D
+:0301D4003743FAB4
+:0301D50037488820
+:0301D600374D138F
+:0301D70037519805
+:0301D80037561C7B
+:0301D900375A9DF5
+:0301DA00375F1B71
+:0301DB00376393F4
+:0301DC0037680978
+:0301DD00376C7C00
+:0301DE003770EA8D
+:0301DF003775541D
+:0301E0003779C0AC
+:0301E100377E2541
+:0301E200378285DC
+:0301E3003786E07C
+:0301E400378B3A1C
+:0301E500378F93BE
+:0301E6003793E765
+:0301E7003798370F
+:0301E800379C85BC
+:0301E90037A0CF6D
+:0301EA0037A51521
+:0301EB0037A959D8
+:0301EC0037AD9894
+:0301ED0037B1D750
+:0301EE0037B60F12
+:0301EF0037BA44D8
+:0301F00037BE799E
+:0301F10037C2A76B
+:0301F20037C6D439
+:0301F30037CAFD0B
+:0301F40037CF25DD
+:0301F50037D347B6
+:0301F60037D76890
+:0301F70037DB846F
+:0301F80037DF9F4F
+:0301F90037E3B435
+:0301FA0037E7C81C
+:0301FB0037EBDA05
+:0301FC0037EFE8F2
+:0301FD0037F3F1E4
+:0301FE0037F7F9D7
+:0301FF0037FC01C9
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fdiv_memoryC2_uid152_invTables_lutmem.hex

@@ -0,0 +1,514 @@
+:020000040000FA
+:020000000FF4FB
+:020001000FDE10
+:020002000FC627
+:020003000FAD3F
+:020004000F9754
+:020005000F7D6D
+:020006000F6881
+:020007000F5197
+:020008000F3BAC
+:020009000F27BF
+:02000A000F0DD8
+:02000B000EF9EC
+:02000C000EE004
+:02000D000ECE15
+:02000E000EB72B
+:02000F000EA041
+:020010000E8C54
+:020011000E7867
+:020012000E627C
+:020013000E4C91
+:020014000E39A3
+:020015000E26B5
+:020016000E10CA
+:020017000DFBDF
+:020018000DEAEF
+:020019000DD305
+:02001A000DC116
+:02001B000DAE28
+:02001C000D9A3B
+:02001D000D874D
+:02001E000D7360
+:02001F000D5F73
+:020020000D4D84
+:020021000D3B95
+:020022000D28A7
+:020023000D16B8
+:020024000D03CA
+:020025000CF0DD
+:020026000CDFED
+:020027000CCFFC
+:020028000CBA10
+:020029000CA920
+:02002A000C9830
+:02002B000C893E
+:02002C000C7551
+:02002D000C6560
+:02002E000C556F
+:02002F000C4380
+:020030000C3290
+:020031000C20A1
+:020032000C12AE
+:020033000C02BD
+:020034000BF2CD
+:020035000BE0DE
+:020036000BCEEF
+:020037000BBFFD
+:020038000BB10A
+:020039000BA119
+:02003A000B9227
+:02003B000B8137
+:02003C000B7245
+:02003D000B6254
+:02003E000B5461
+:02003F000B4371
+:020040000B367D
+:020041000B278B
+:020042000B1998
+:020043000B09A7
+:020044000AF9B7
+:020045000AEEC1
+:020046000ADCD2
+:020047000ACEDF
+:020048000AC1EB
+:020049000AB3F8
+:02004A000AA505
+:02004B000A9712
+:02004C000A8A1E
+:02004D000A7C2B
+:02004E000A6E38
+:02004F000A6243
+:020050000A5351
+:020051000A445F
+:020052000A386A
+:020053000A2C75
+:020054000A1F81
+:020055000A138C
+:020056000A049A
+:0200570009F9A5
+:0200580009EBB2
+:0200590009DEBE
+:02005A0009D3C8
+:02005B0009C6D4
+:02005C0009BADF
+:02005D0009AEEA
+:02005E0009A3F4
+:02005F00099204
+:0200600009870E
+:02006100097B19
+:02006200096F24
+:0200630009652D
+:02006400095839
+:02006500094E42
+:0200660009424D
+:02006700093559
+:02006800092A63
+:0200690009206C
+:02006A00091279
+:02006B00090981
+:02006C0008FF8B
+:02006D0008F495
+:02006E0008E7A1
+:02006F0008DDAA
+:0200700008CFB7
+:0200710008C7BE
+:0200720008BACA
+:0200730008B1D2
+:0200740008A8DA
+:02007500089BE6
+:020076000892EE
+:020077000887F8
+:02007800087C02
+:0200790008730A
+:02007A00086814
+:02007B00085E1D
+:02007C00085426
+:02007D00084A2F
+:02007E00084137
+:02007F00083641
+:02008000082C4A
+:02008100082352
+:0200820008195B
+:02008300081063
+:0200840008056D
+:0200850007FC76
+:0200860007F37E
+:0200870007EA86
+:0200880007E28D
+:0200890007D599
+:02008A0007CDA0
+:02008B0007C6A6
+:02008C0007BDAE
+:02008D0007B1B9
+:02008E0007A8C1
+:02008F00079FC9
+:020090000796D1
+:02009100078ED8
+:020092000785E0
+:02009300077BE9
+:020094000773F0
+:02009500076CF6
+:020096000765FC
+:02009700075907
+:0200980007520D
+:02009900074915
+:02009A0007411C
+:02009B00073824
+:02009C00072E2D
+:02009D00072832
+:02009E00071D3C
+:02009F00071741
+:0200A000070F48
+:0200A10007074F
+:0200A200070154
+:0200A30006FA5B
+:0200A40006ED67
+:0200A50006E76C
+:0200A60006E171
+:0200A70006D77A
+:0200A80006D17F
+:0200A90006CA85
+:0200AA0006C28C
+:0200AB0006BA93
+:0200AC0006B29A
+:0200AD0006AC9F
+:0200AE0006A3A7
+:0200AF00069BAE
+:0200B0000695B3
+:0200B100068CBB
+:0200B2000685C1
+:0200B3000680C5
+:0200B4000679CB
+:0200B5000673D0
+:0200B6000669D9
+:0200B7000661E0
+:0200B800065DE3
+:0200B9000652ED
+:0200BA00064CF2
+:0200BB000645F8
+:0200BC00063EFE
+:0200BD00063803
+:0200BE00063208
+:0200BF00062C0D
+:0200C000062612
+:0200C100062017
+:0200C200061620
+:0200C300061223
+:0200C40006072D
+:0200C500060231
+:0200C60005FC37
+:0200C70005F63C
+:0200C80005EF42
+:0200C90005E947
+:0200CA0005E34C
+:0200CB0005DE50
+:0200CC0005D459
+:0200CD0005CF5D
+:0200CE0005CA61
+:0200CF0005C565
+:0200D00005BE6B
+:0200D10005B870
+:0200D20005B077
+:0200D30005AC7A
+:0200D40005A67F
+:0200D500059F85
+:0200D60005998A
+:0200D70005938F
+:0200D800058F92
+:0200D900058799
+:0200DA0005829D
+:0200DB00057EA0
+:0200DC000579A4
+:0200DD000573A9
+:0200DE00056BB0
+:0200DF000566B4
+:0200E000055FBA
+:0200E100055ABE
+:0200E2000554C3
+:0200E300054EC8
+:0200E400054ACB
+:0200E5000543D1
+:0200E600053DD6
+:0200E700053AD8
+:0200E8000535DC
+:0200E900052EE2
+:0200EA000528E7
+:0200EB000525E9
+:0200EC000522EB
+:0200ED000519F3
+:0200EE000516F5
+:0200EF000510FA
+:0200F000050900
+:0200F100050602
+:0200F200050106
+:0200F30004FB0C
+:0200F40004F610
+:0200F50004F015
+:0200F60004EA1A
+:0200F70004E61D
+:0200F80004E121
+:0200F90004DD24
+:0200FA0004D927
+:0200FB0004D42B
+:0200FC0004D02E
+:0200FD0004CA33
+:0200FE0004C438
+:0200FF0004C03B
+:0201000004BC3D
+:0201010004B543
+:0201020004B047
+:0201030004AD49
+:0201040004A84D
+:0201050004A252
+:02010600049D56
+:02010700049A58
+:0201080004975A
+:0201090004915F
+:02010A00048C63
+:02010B00048866
+:02010C00048568
+:02010D0004816B
+:02010E00047D6E
+:02010F00047674
+:02011000047376
+:02011100047078
+:02011200046A7D
+:02011300046482
+:02011400046283
+:02011500045B89
+:0201160004588B
+:0201170004558D
+:02011800045190
+:02011900044C94
+:02011A00044897
+:02011B0004439B
+:02011C00043F9E
+:02011D00043CA0
+:02011E000438A3
+:02011F000433A7
+:02012000042EAB
+:02012100042CAC
+:02012200042AAD
+:020123000425B1
+:020124000420B5
+:02012500041DB7
+:020126000419BA
+:020127000414BE
+:020128000411C0
+:02012900040CC4
+:02012A000408C7
+:02012B000406C8
+:02012C000401CC
+:02012D0003FDD0
+:02012E0003FAD2
+:02012F0003F6D5
+:0201300003F1D9
+:0201310003EEDB
+:0201320003EADE
+:0201330003E6E1
+:0201340003E3E3
+:0201350003DFE6
+:0201360003DAEA
+:0201370003D8EB
+:0201380003D7EB
+:0201390003CFF2
+:02013A0003CCF4
+:02013B0003CAF5
+:02013C0003C8F6
+:02013D0003C3FA
+:02013E0003BFFD
+:02013F0003BCFF
+:0201400003B802
+:0201410003B504
+:0201420003B107
+:0201430003AD0A
+:0201440003AB0B
+:0201450003A90C
+:0201460003A50F
+:0201470003A112
+:02014800039E14
+:02014900039C15
+:02014A00039818
+:02014B0003951A
+:02014C0003911D
+:02014D00038C21
+:02014E00038A22
+:02014F00038625
+:02015000038426
+:02015100038227
+:02015200037E2A
+:02015300037B2C
+:0201540003782E
+:02015500037530
+:02015600037232
+:02015700036D36
+:02015800036B37
+:02015900036938
+:02015A0003663A
+:02015B0003613E
+:02015C00035F3F
+:02015D00035E3F
+:02015E00035A42
+:02015F00035546
+:02016000035248
+:02016100034F4A
+:02016200034E4A
+:02016300034C4B
+:0201640003494D
+:02016500034451
+:02016600034153
+:02016700033F54
+:02016800033D55
+:02016900033B56
+:02016A00033858
+:02016B0003345B
+:02016C0003315D
+:02016D00032E5F
+:02016E00032A62
+:02016F00032863
+:02017000032763
+:02017100032564
+:02017200031F69
+:02017300031E69
+:02017400031A6C
+:0201750003176E
+:02017600031371
+:02017700031172
+:02017800031072
+:02017900030E73
+:02017A00030B75
+:02017B00030877
+:02017C00030579
+:02017D0003027B
+:02017E0003007C
+:02017F0002FF7D
+:0201800002FD7E
+:0201810002F981
+:0201820002F584
+:0201830002F385
+:0201840002F186
+:0201850002EF87
+:0201860002EB8A
+:0201870002E88C
+:0201880002E78C
+:0201890002E68C
+:02018A0002E38E
+:02018B0002E090
+:02018C0002DF90
+:02018D0002D995
+:02018E0002D994
+:02018F0002D894
+:0201900002D398
+:0201910002D199
+:0201920002CF9A
+:0201930002CE9A
+:0201940002C89F
+:0201950002C6A0
+:0201960002C3A2
+:0201970002C1A3
+:0201980002C0A3
+:0201990002BEA4
+:02019A0002BBA6
+:02019B0002BBA5
+:02019C0002BAA5
+:02019D0002B7A7
+:02019E0002B4A9
+:02019F0002B1AB
+:0201A00002ADAE
+:0201A10002ACAE
+:0201A20002ABAE
+:0201A30002A8B0
+:0201A40002A5B2
+:0201A50002A3B3
+:0201A60002A3B2
+:0201A700029EB6
+:0201A800029CB7
+:0201A900029AB8
+:0201AA000298B9
+:0201AB000295BB
+:0201AC000292BD
+:0201AD000292BC
+:0201AE000291BC
+:0201AF00028FBD
+:0201B000028DBE
+:0201B100028AC0
+:0201B2000289C0
+:0201B3000287C1
+:0201B4000284C3
+:0201B5000281C5
+:0201B600027FC6
+:0201B700027CC8
+:0201B800027BC8
+:0201B900027BC7
+:0201BA000278C9
+:0201BB000277C9
+:0201BC000276C9
+:0201BD000272CC
+:0201BE00026ECF
+:0201BF00026DCF
+:0201C000026DCE
+:0201C100026BCF
+:0201C2000267D2
+:0201C3000266D2
+:0201C4000265D2
+:0201C5000262D4
+:0201C6000261D4
+:0201C7000261D3
+:0201C800025DD6
+:0201C900025BD7
+:0201CA00025BD6
+:0201CB000258D8
+:0201CC000255DA
+:0201CD000253DB
+:0201CE000251DC
+:0201CF000252DA
+:0201D000024EDD
+:0201D100024DDD
+:0201D200024BDE
+:0201D3000249DF
+:0201D4000246E1
+:0201D5000244E2
+:0201D6000243E2
+:0201D7000243E1
+:0201D8000241E2
+:0201D900023EE4
+:0201DA00023CE5
+:0201DB00023BE5
+:0201DC000239E6
+:0201DD000237E7
+:0201DE000236E7
+:0201DF000236E6
+:0201E0000230EB
+:0201E100022EEC
+:0201E200022EEB
+:0201E300022FE9
+:0201E400022DEA
+:0201E500022AEC
+:0201E6000228ED
+:0201E7000227ED
+:0201E8000224EF
+:0201E9000223EF
+:0201EA000221F0
+:0201EB000220F0
+:0201EC00021EF1
+:0201ED00021BF3
+:0201EE00021BF2
+:0201EF00021BF1
+:0201F0000218F3
+:0201F1000217F3
+:0201F2000216F3
+:0201F3000214F4
+:0201F4000212F5
+:0201F5000211F5
+:0201F600020FF6
+:0201F700020EF6
+:0201F800020CF7
+:0201F900020CF6
+:0201FA00020AF7
+:0201FB000207F9
+:0201FC000206F9
+:0201FD000205F9
+:0201FE000204F9
+:0201FF0001FFFE
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv

@@ -0,0 +1,74 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_fmadd
+// SystemVerilog created on Sun Dec 27 09:47:20 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_fmadd (
+    input wire [31:0] a,
+    input wire [31:0] b,
+    input wire [31:0] c,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [31:0] fpMultAddTest_impl_ax0;
+    wire [31:0] fpMultAddTest_impl_ay0;
+    wire [31:0] fpMultAddTest_impl_az0;
+    wire [31:0] fpMultAddTest_impl_q0;
+    wire fpMultAddTest_impl_reset0;
+    wire fpMultAddTest_impl_fpMultAddTest_impl_ena0;
+
+
+    // fpMultAddTest_impl(FPCOLUMN,5)@0
+    // out q0@4
+    assign fpMultAddTest_impl_ax0 = c;
+    assign fpMultAddTest_impl_ay0 = b;
+    assign fpMultAddTest_impl_az0 = a;
+    assign fpMultAddTest_impl_reset0 = areset;
+    assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0];
+    twentynm_fp_mac #(
+        .operation_mode("sp_mult_add"),
+        .use_chainin("false"),
+        .ax_clock("0"),
+        .ay_clock("0"),
+        .az_clock("0"),
+        .mult_pipeline_clock("0"),
+        .adder_input_clock("0"),
+        .ax_chainin_pl_clock("0"),
+        .output_clock("0")
+    ) fpMultAddTest_impl_DSP0 (
+        .aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
+        .clk({1'b0,1'b0,clk}),
+        .ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }),
+        .ax(fpMultAddTest_impl_ax0),
+        .ay(fpMultAddTest_impl_ay0),
+        .az(fpMultAddTest_impl_az0),
+        .resulta(fpMultAddTest_impl_q0),
+        .accumulate(),
+        .chainin(),
+        .chainout()
+    );
+
+    // xOut(GPOUT,4)@4
+    assign q = fpMultAddTest_impl_q0;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_fmsub.sv

@@ -0,0 +1,75 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_fmsub
+// SystemVerilog created on Sun Dec 27 07:07:02 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_fmsub (
+    input wire [31:0] a,
+    input wire [31:0] b,
+    input wire [31:0] c,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [31:0] fpMultAddTest_impl_ax0;
+    wire [31:0] fpMultAddTest_impl_ay0;
+    wire [31:0] fpMultAddTest_impl_az0;
+    wire [31:0] fpMultAddTest_impl_q0;
+    wire fpMultAddTest_impl_reset0;
+    wire fpMultAddTest_impl_fpMultAddTest_impl_ena0;
+
+
+    // fpMultAddTest_impl(FPCOLUMN,5)@0
+    // out q0@4
+    assign fpMultAddTest_impl_ax0 = c;
+    assign fpMultAddTest_impl_ay0 = b;
+    assign fpMultAddTest_impl_az0 = a;
+    assign fpMultAddTest_impl_reset0 = areset;
+    assign fpMultAddTest_impl_fpMultAddTest_impl_ena0 = en[0];
+    twentynm_fp_mac #(
+        .operation_mode("sp_mult_add"),        
+        .adder_subtract("true"),
+        .use_chainin("false"),
+        .ax_clock("0"),
+        .ay_clock("0"),
+        .az_clock("0"),
+        .mult_pipeline_clock("0"),
+        .adder_input_clock("0"),
+        .ax_chainin_pl_clock("0"),
+        .output_clock("0")
+    ) fpMultAddTest_impl_DSP0 (
+        .aclr({ fpMultAddTest_impl_reset0, fpMultAddTest_impl_reset0 }),
+        .clk({1'b0,1'b0,clk}),
+        .ena({ 1'b0, 1'b0, fpMultAddTest_impl_fpMultAddTest_impl_ena0 }),
+        .ax(fpMultAddTest_impl_ax0),
+        .ay(fpMultAddTest_impl_ay0),
+        .az(fpMultAddTest_impl_az0),
+        .resulta(fpMultAddTest_impl_q0),
+        .accumulate(),
+        .chainin(),
+        .chainout()
+    );
+
+    // xOut(GPOUT,4)@4
+    assign q = fpMultAddTest_impl_q0;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_fmul.sv

@@ -0,0 +1,67 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_fmul
+// SystemVerilog created on Sun Dec 27 09:47:20 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_fmul (
+    input wire [31:0] a,
+    input wire [31:0] b,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [31:0] fpMulTest_impl_ay0;
+    wire [31:0] fpMulTest_impl_az0;
+    wire [31:0] fpMulTest_impl_q0;
+    wire fpMulTest_impl_reset0;
+    wire fpMulTest_impl_fpMulTest_impl_ena0;
+
+
+    // fpMulTest_impl(FPCOLUMN,5)@0
+    // out q0@3
+    assign fpMulTest_impl_ay0 = b;
+    assign fpMulTest_impl_az0 = a;
+    assign fpMulTest_impl_reset0 = areset;
+    assign fpMulTest_impl_fpMulTest_impl_ena0 = en[0];
+    twentynm_fp_mac #(
+        .operation_mode("sp_mult"),
+        .ay_clock("0"),
+        .az_clock("0"),
+        .mult_pipeline_clock("0"),
+        .output_clock("0")
+    ) fpMulTest_impl_DSP0 (
+        .aclr({ fpMulTest_impl_reset0, fpMulTest_impl_reset0 }),
+        .clk({1'b0,1'b0,clk}),
+        .ena({ 1'b0, 1'b0, fpMulTest_impl_fpMulTest_impl_ena0 }),
+        .ay(fpMulTest_impl_ay0),
+        .az(fpMulTest_impl_az0),
+        .resulta(fpMulTest_impl_q0),
+        .accumulate(),
+        .ax(),
+        .chainin(),
+        .chainout()
+    );
+
+    // xOut(GPOUT,4)@3
+    assign q = fpMulTest_impl_q0;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC0_uid88_sqrtTables_lutmem.hex

@@ -0,0 +1,258 @@
+:020000040000FA
+:0400000008000004F0
+:040001000807FC08E8
+:04000200080FF024CF
+:040003000817DC6F8F
+:04000400081FC0FF12
+:0400050008279DEC3F
+:04000600082F734C00
+:040007000837413342
+:04000800083F07B7EF
+:040009000846C6EEF1
+:04000A00084E7EEB33
+:04000B0008562FC2A2
+:04000C00085DD9882A
+:04000D0008657C4FB7
+:04000E00086D182B36
+:04000F000874AD2E96
+:04001000087C3B6BC2
+:040011000883C2F3AB
+:04001200088B43D83C
+:040013000892BE2D64
+:04001400089A320113
+:0400150008A19F6639
+:0400160008A9066DC2
+:0400170008B06725A1
+:0400180008B7C19EC6
+:0400190008BF15E91E
+:04001A0008C664159B
+:04001B0008CDAC312F
+:04001C0008D4EE4CCA
+:04001D0008DC2A755C
+:04001E0008E360BAD9
+:04001F0008EA912931
+:0400200008F1BBD256
+:0400210008F8E0C13A
+:0400220009000004CD
+:04002300090719A907
+:04002400090E2DBCD8
+:0400250009153C4C31
+:04002600091C456408
+:04002700092349114F
+:04002800092A4761F9
+:040029000931405EFB
+:04002A000938341548
+:04002B00093F2292D5
+:04002C0009460BE195
+:04002D00094CF00D7D
+:04002E000953CF2182
+:04002F00095AA92998
+:0400300009617E31B3
+:0400310009684E42CA
+:04003200096F1967D2
+:040033000975DFACC0
+:04003400097CA11A88
+:0400350009835DBC22
+:04003600098A159C82
+:040037000990C8C59F
+:040038000997773F6E
+:04003900099E2115E6
+:04003A0009A4C650FF
+:04003B0009AB66FAAD
+:04003C0009B2031CE6
+:04003D0009B89AC0A4
+:04003E0009BF2DEEDB
+:04003F0009C5BCB083
+:0400400009CC470E92
+:0400410009D2CD1102
+:0400420009D94EC3C7
+:0400430009DFCC2ADB
+:0400440009E6455133
+:0400450009ECBA3FC9
+:0400460009F32AFC94
+:0400470009F997908C
+:040048000A000004A6
+:040049000A06645FE0
+:04004A000A0CC4AA2E
+:04004B000A1320EC88
+:04004C000A19792CE8
+:04004D000A1FCD7247
+:04004E000A261DC69B
+:04004F000A2C6A2FDE
+:040050000A32B2B40A
+:040051000A38F75C16
+:040052000A3F382EFB
+:040053000A457532B3
+:040054000A4BAE6F36
+:040055000A51E3EA7F
+:040056000A5815AC83
+:040057000A5E43BA40
+:040058000A646E1BAD
+:040059000A6A94D6C5
+:04005A000A70B7F180
+:04005B000A76D773D7
+:04005C000A7CF362C5
+:04005D000A830BC443
+:04005E000A89209F4C
+:04005F000A8F31F9DA
+:040060000A953FD9E5
+:040061000A9B4A4468
+:040062000AA151405E
+:040063000AA754D4C0
+:040064000AAD550488
+:040065000AB351D7B2
+:040066000AB94B5236
+:040067000ABF417A11
+:040068000AC534563B
+:040069000ACB23EBB0
+:04006A000AD1103E69
+:04006B000AD6F95464
+:04006C000ADCDF3398
+:04006D000AE2C1E002
+:04006E000AE8A15F9C
+:04006F000AEE7DB860
+:040070000AF456ED4B
+:040071000AFA2D0555
+:040072000B0000047B
+:040073000B05CFEFBB
+:040074000B0B9CCC0A
+:040075000B11669E67
+:040076000B172D6BCC
+:040077000B1CF13736
+:040078000B22B2079E
+:040079000B286FDF02
+:04007A000B2E2AC55A
+:04007B000B33E2BDA4
+:04007C000B3997CBDA
+:04007D000B3F49F3F9
+:04007E000B44F93AFC
+:04007F000B4AA5A5DE
+:040080000B504F379B
+:040081000B5B99E498
+:040082000B66D962CE
+:040083000B720DD21D
+:040084000B7D375564
+:040085000B88560A84
+:040086000B936A105E
+:040087000B9E7387D2
+:040088000BA9728BC3
+:040089000BB4673B12
+:04008A000BBF51B3A4
+:04008B000BCA32105A
+:04008C000BD5086D1B
+:04008D000BDFD4E6CB
+:04008E000BEA97964C
+:04008F000BF5509885
+:040090000C0000045C
+:040091000C0AA5F5BB
+:040092000C15428483
+:040093000C1FD5CA9F
+:040094000C2A5FDEF5
+:040095000C34E0D86F
+:040096000C3F58D1F2
+:040097000C49C7DE6B
+:040098000C542E17BF
+:040099000C5E8B91DD
+:04009A000C68E063AB
+:04009B000C732CA313
+:04009C000C7D706502
+:04009D000C87ABBE63
+:04009E000C91DEC320
+:04009F000C9C098824
+:0400A0000CA62C225C
+:0400A1000CB046A2B7
+:0400A2000CBA591E1D
+:0400A3000CC463A77F
+:0400A4000CCE6651C7
+:0400A5000CD8612EE4
+:0400A6000CE2544FC5
+:0400A7000CEC3FC856
+:0400A8000CF623A986
+:0400A9000D00000442
+:0400AA000D09D4EA7E
+:0400AB000D13A26B24
+:0400AC000D1D689925
+:0400AD000D27278470
+:0400AE000D30DF3BF7
+:0400AF000D3A8FCEA9
+:0400B0000D44394E74
+:0400B1000D4DDBCA4C
+:0400B2000D5777501F
+:0400B3000D610BF0E0
+:0400B4000D6A99B97F
+:0400B5000D7420B9ED
+:0400B6000D7DA0FE1E
+:0400B7000D871A9700
+:0400B8000D908D9288
+:0400B9000D99F9FDA7
+:0400BA000DA35FE44F
+:0400BB000DACBF5673
+:0400BC000DB6186005
+:0400BD000DBF6B0FF9
+:0400BE000DC8B76F43
+:0400BF000DD1FD8ED4
+:0400C0000DDB3D789F
+:0400C1000DE4773A99
+:0400C2000DEDAADFB7
+:0400C3000DF6D874EA
+:0400C4000E00000426
+:0400C5000E09219C63
+:0400C6000E123D4792
+:0400C7000E1B5311A8
+:0400C8000E2463049B
+:0400C9000E2D6D2D5E
+:0400CA000E367195E8
+:0400CB000E3F70492B
+:0400CC000E4869531E
+:0400CD000E515CBDB7
+:0400CE000E5A4A92EA
+:0400CF000E6332DCAE
+:0400D0000E6C15A6F7
+:0400D1000E74F2FABD
+:0400D2000E7DCAE2F3
+:0400D3000E869D6791
+:0400D4000E8F6A948D
+:0400D5000E983272DD
+:0400D6000EA0F50B78
+:0400D7000EA9B26854
+:0400D8000EB26A9367
+:0400D9000EBB1D94A9
+:0400DA000EC3CB7610
+:0400DB000ECC744093
+:0400DC000ED517FC2A
+:0400DD000EDDB6B2CC
+:0400DE000EE6506C6E
+:0400DF000EEEE5320A
+:0400E0000EF7750D95
+:0400E1000F00000408
+:0400E2000F0886215C
+:0400E3000F11076B87
+:0400E4000F1983EA83
+:0400E5000F21FBA844
+:0400E6000F2A6EAAC5
+:0400E7000F32DCFBFD
+:0400E8000F3B46A1E3
+:0400E9000F43ABA472
+:0400EA000F4C0C0BA0
+:0400EB000F5467DF68
+:0400EC000F5CBF27BF
+:0400ED000F6511E9A1
+:0400EE000F6D602E04
+:0400EF000F75A9FDE3
+:0400F0000F7DEF5D34
+:0400F1000F863054F2
+:0400F2000F8E6CEB16
+:0400F3000F96A52798
+:0400F4000F9ED91072
+:0400F5000FA708AC9D
+:0400F6000FAF340311
+:0400F7000FB75B1BC9
+:0400F8000FBF7DFABF
+:0400F9000FC79CA7EA
+:0400FA000FCFB72944
+:0400FB000FD7CD85C9
+:0400FC000FDFDFC370
+:0400FD000FE7EDE933
+:0400FE000FEFF7FC0D
+:0400FF000FF7FE03F6
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC1_uid91_sqrtTables_lutmem.hex

@@ -0,0 +1,258 @@
+:020000040000FA
+:0300000007FFFEF9
+:0300010007F809F4
+:0300020007F02DD7
+:0300030007E866A5
+:0300040007E0BA58
+:0300050007D922F6
+:0300060007D19C83
+:0300070007CA31F4
+:0300080007C2D953
+:0300090007BB949E
+:03000A0007B465D3
+:03000B0007AD4AF4
+:03000C0007A64103
+:03000D00079F4DFD
+:03000E0007986AE6
+:03000F0007919BBB
+:03001000078ADB81
+:030011000784322F
+:03001200077D9ACD
+:0300130007770F5D
+:03001400077099D9
+:03001500076A3344
+:030016000763D9A4
+:03001700075D94EE
+:0300180007575F28
+:0300190007513854
+:03001A00074B1F72
+:03001B0007451680
+:03001C00073F1E7D
+:03001D000739316F
+:03001E000733564F
+:03001F00072D8A20
+:030020000727C7E8
+:030021000722159E
+:03002200071C7048
+:030023000716D9E4
+:0300240007115071
+:03002500070BD0F6
+:030026000706606A
+:030027000700FED1
+:0300280006FBA133
+:0300290006F65583
+:03002A0006F116C6
+:03002B0006EBE2FF
+:03002C0006E6B82D
+:03002D0006E19C4D
+:03002E0006DC8D60
+:03002F0006D7866B
+:0300300006D2886D
+:0300310006CD9861
+:0300320006C8B34A
+:0300330006C3D62B
+:0300340006BF06FE
+:0300350006BA40C8
+:0300360006B58488
+:0300370006B0CD43
+:0300380006AC24EF
+:0300390006A78592
+:03003A0006A2F02B
+:03003B00069E64BA
+:03003C000699E141
+:03003D00069566BF
+:03003E000690F633
+:03003F00068C8D9F
+:0300400006882F00
+:030041000683D95A
+:03004200067F8AAC
+:03004300067B46F3
+:0300440006770834
+:030045000672D16F
+:03004600066EA59E
+:03004700066A82C4
+:03004800066666E3
+:03004900066253F9
+:03004A00065E440B
+:03004B00065A3E14
+:03004C0006564114
+:03004D0006524C0C
+:03004E00064E5CFF
+:03004F00064A73EB
+:03005000064693CE
+:030051000642BBA9
+:03005200063EEB7C
+:03005300063B1F4A
+:0300540006375A12
+:0300550006339DD2
+:03005600062FE58D
+:03005700062C363E
+:0300580006288DEA
+:030059000624EB8F
+:03005A0006214F2D
+:03005B00061DB7C8
+:03005C00061A265B
+:03005D0006169BE9
+:03005E000613186E
+:03005F00060F9CED
+:03006000060C2467
+:030061000608B3DB
+:0300620006054848
+:030063000601E0B3
+:0300640005FE8016
+:0300650005FB2573
+:0300660005F7D0CB
+:0300670005F4831A
+:0300680005F13867
+:0300690005EDF1B1
+:03006A0005EAB1F3
+:03006B0005E7782E
+:03006C0005E44266
+:03006D0005E11298
+:03006E0005DDEDC0
+:03006F0005DAC4EB
+:0300700005D7A60B
+:0300710005D48A29
+:0300720005D17441
+:0300730005CE6552
+:0300740005CB5465
+:0300750005C84D6E
+:0300760005C54974
+:0300770005C24B74
+:0300780005BF536E
+:0300790005BC6063
+:03007A0005B96E57
+:03007B0005B68047
+:03007C0005B39831
+:03007D0005B0B714
+:03007E0005ADD9F4
+:03007F0005AAFED1
+:030080000B504DD5
+:030081000B450C20
+:030082000B39EE49
+:030083000B2EF34E
+:030084000B241238
+:030085000B1955FF
+:030086000B0EB8A6
+:030087000B043433
+:030088000AF9D39F
+:030089000AEF8BF0
+:03008A000AE56321
+:03008B000ADB5439
+:03008C000AD16432
+:03008D000AC78E11
+:03008E000ABDD3D5
+:03008F000AB42F81
+:030090000AAAA910
+:030091000AA13B86
+:030092000A97E6E4
+:030093000A8EA52D
+:030094000A858159
+:030095000A7C756D
+:030096000A737B6F
+:030097000A6A9D55
+:030098000A61D228
+:030099000A5921E0
+:03009A000A508485
+:03009B000A47FA17
+:03009C000A3F8791
+:03009D000A372AF5
+:03009E000A2EE146
+:03009F000A26AC82
+:0300A0000A1E86AF
+:0300A1000A1679C3
+:0300A2000A0E7CC7
+:0300A3000A0695B5
+:0300A40009FEBF93
+:0300A50009F6FA5F
+:0300A60009EF4A15
+:0300A70009E7A8BE
+:0300A80009E01A52
+:0300A90009D89CD7
+:0300AA0009D12F4A
+:0300AB0009C9D5AB
+:0300AC0009C289FD
+:0300AD0009BB4A42
+:0300AE0009B42072
+:0300AF0009AD0692
+:0300B00009A5FBA4
+:0300B100099EFBAA
+:0300B20009980F9B
+:0300B30009913080
+:0300B400098A5F57
+:0300B50009839E1E
+:0300B600097CEDD5
+:0300B7000976487F
+:0300B800096FAF1E
+:0300B900096925AD
+:0300BA000962AB2D
+:0300BB00095C3CA1
+:0300BC000955D90A
+:0300BD00094F8464
+:0300BE0009493EAF
+:0300BF00094302F0
+:0300C000093CD424
+:0300C1000936AE4F
+:0300C20009309A68
+:0300C300092A8E79
+:0300C4000924917B
+:0300C500091E9E73
+:0300C6000918B75F
+:0300C7000912DA41
+:0300C800090D0B14
+:0300C900090745DF
+:0300CA0009018D9C
+:0300CB0008FBDB54
+:0300CC0008F635FE
+:0300CD0008F09B9D
+:0300CE0008EB0C30
+:0300CF0008E588B9
+:0300D00008E00D38
+:0300D10008DA9BAF
+:0300D20008D5341A
+:0300D30008CFD87B
+:0300D40008CA85D2
+:0300D50008C53B20
+:0300D60008BFFA66
+:0300D70008BAC3A1
+:0300D80008B595D3
+:0300D90008B070FC
+:0300DA0008AB521E
+:0300DB0008A64034
+:0300DC0008A13741
+:0300DD00089C3844
+:0300DE0008974040
+:0300DF0008924F35
+:0300E000088D6622
+:0300E10008888903
+:0300E2000883AFE1
+:0300E300087EE1B3
+:0300E400087A1E79
+:0300E50008755B40
+:0300E6000870A9F6
+:0300E700086BF9AA
+:0300E80008675155
+:0300E9000862B3F7
+:0300EA00085E1D90
+:0300EB0008598C25
+:0300EC00085503B1
+:0300ED0008508434
+:0300EE00084C0AB1
+:0300EF000847952A
+:0300F00008432999
+:0300F100083EC600
+:0300F200083A6564
+:0300F30008360FBD
+:0300F4000831C010
+:0300F500082D785B
+:0300F600082934A2
+:0300F7000824F8E2
+:0300F8000820C419
+:0300F900081C964A
+:0300FA0008186E75
+:0300FB0008144E98
+:0300FC00081031B8
+:0300FD00080C1AD2
+:0300FE0008080BE4
+:0300FF00080402F0
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fsqrt_memoryC2_uid94_sqrtTables_lutmem.hex

@@ -0,0 +1,258 @@
+:020000040000FA
+:020000000C06EC
+:020001000C13DE
+:020002000C1DD3
+:020003000C2AC5
+:020004000C33BB
+:020005000C3DB0
+:020006000C4BA1
+:020007000C5398
+:020008000C5E8C
+:020009000C6980
+:02000A000C7276
+:02000B000C7C6B
+:02000C000C8660
+:02000D000C8F56
+:02000E000C994B
+:02000F000CA142
+:020010000CAD35
+:020011000CB32E
+:020012000CBB25
+:020013000CC51A
+:020014000CCC12
+:020015000CD30A
+:020016000CDFFD
+:020017000CE5F6
+:020018000CECEE
+:020019000CF4E5
+:02001A000CFDDB
+:02001B000D05D1
+:02001C000D0ACB
+:02001D000D14C0
+:02001E000D19BA
+:02001F000D1FB3
+:020020000D28A9
+:020021000D2EA2
+:020022000D359A
+:020023000D3A94
+:020024000D408D
+:020025000D4884
+:020026000D4D7E
+:020027000D5179
+:020028000D5C6D
+:020029000D6266
+:02002A000D6760
+:02002B000D6D59
+:02002C000D7451
+:02002D000D784C
+:02002E000D7B48
+:02002F000D8240
+:020030000D8938
+:020031000D8D33
+:020032000D922D
+:020033000D9826
+:020034000D9C21
+:020035000DA01C
+:020036000DA417
+:020037000DAD0D
+:020038000DB207
+:020039000DB602
+:02003A000DBAFD
+:02003B000DBEF8
+:02003C000DC3F2
+:02003D000DC8EC
+:02003E000DCCE7
+:02003F000DD1E1
+:020040000DD4DD
+:020041000DD9D7
+:020042000DDDD2
+:020043000DE1CD
+:020044000DE5C8
+:020045000DECC0
+:020046000DEFBC
+:020047000DF2B8
+:020048000DF5B4
+:020049000DF8B0
+:02004A000DFEA9
+:02004B000E02A3
+:02004C000E059F
+:02004D000E089B
+:02004E000E0D95
+:02004F000E128F
+:020050000E158B
+:020051000E1788
+:020052000E1985
+:020053000E1E7F
+:020054000E217B
+:020055000E2576
+:020056000E2971
+:020057000E2B6E
+:020058000E2E6A
+:020059000E3067
+:02005A000E3363
+:02005B000E385D
+:02005C000E3C58
+:02005D000E4053
+:02005E000E4250
+:02005F000E444D
+:020060000E4749
+:020061000E4946
+:020062000E4C42
+:020063000E503D
+:020064000E5339
+:020065000E5635
+:020066000E5832
+:020067000E5930
+:020068000E5D2B
+:020069000E6225
+:02006A000E6521
+:02006B000E671E
+:02006C000E6B19
+:02006D000E6E15
+:02006E000E6B17
+:02006F000E7110
+:020070000E720E
+:020071000E750A
+:020072000E7707
+:020073000E7706
+:020074000E7EFE
+:020075000E80FB
+:020076000E83F7
+:020077000E85F4
+:020078000E85F3
+:020079000E86F1
+:02007A000E8AEC
+:02007B000E8EE7
+:02007C000E90E4
+:02007D000E90E3
+:02007E000E92E0
+:02007F000E94DD
+:020080000A6014
+:020081000A7201
+:020082000A82F0
+:020083000A8FE2
+:020084000AA3CD
+:020085000AB1BE
+:020086000ABEB0
+:020087000AD09D
+:020088000ADC90
+:020089000AED7E
+:02008A000AF971
+:02008B000B095F
+:02008C000B1552
+:02008D000B2244
+:02008E000B2E37
+:02008F000B3D27
+:020090000B481B
+:020091000B540E
+:020092000B5F02
+:020093000B6FF1
+:020094000B79E6
+:020095000B83DB
+:020096000B92CB
+:020097000B9BC1
+:020098000BA8B3
+:020099000BB1A9
+:02009A000BBC9D
+:02009B000BC890
+:02009C000BD285
+:02009D000BDB7B
+:02009E000BE471
+:02009F000BED67
+:0200A0000BFA59
+:0200A1000C034E
+:0200A2000C0D43
+:0200A3000C153A
+:0200A4000C1D31
+:0200A5000C2726
+:0200A6000C2F1D
+:0200A7000C3912
+:0200A8000C4109
+:0200A9000C4AFF
+:0200AA000C52F6
+:0200AB000C59EE
+:0200AC000C61E5
+:0200AD000C6DD8
+:0200AE000C73D1
+:0200AF000C7AC9
+:0200B0000C80C2
+:0200B1000C8BB6
+:0200B2000C91AF
+:0200B3000C99A6
+:0200B4000CA19D
+:0200B5000CA796
+:0200B6000CAC90
+:0200B7000CB388
+:0200B8000CBC7E
+:0200B9000CC277
+:0200BA000CC771
+:0200BB000CCE69
+:0200BC000CD660
+:0200BD000CDC59
+:0200BE000CE153
+:0200BF000CE84B
+:0200C0000CED45
+:0200C1000CF73A
+:0200C2000CFA36
+:0200C3000D022C
+:0200C4000D0726
+:0200C5000D0D1F
+:0200C6000D1318
+:0200C7000D1911
+:0200C8000D1E0B
+:0200C9000D2305
+:0200CA000D2700
+:0200CB000D2FF7
+:0200CC000D35F0
+:0200CD000D3AEA
+:0200CE000D3EE5
+:0200CF000D42E0
+:0200D0000D47DA
+:0200D1000D4DD3
+:0200D2000D51CE
+:0200D3000D55C9
+:0200D4000D59C4
+:0200D5000D5EBE
+:0200D6000D63B8
+:0200D7000D68B2
+:0200D8000D6CAD
+:0200D9000D72A6
+:0200DA000D789F
+:0200DB000D7C9A
+:0200DC000D7F96
+:0200DD000D8292
+:0200DE000D868D
+:0200DF000D8C86
+:0200E0000D9180
+:0200E1000D937D
+:0200E2000D9B74
+:0200E3000D9E70
+:0200E4000D9F6E
+:0200E5000DA864
+:0200E6000DA863
+:0200E7000DAD5D
+:0200E8000DB257
+:0200E9000DB454
+:0200EA000DB750
+:0200EB000DBC4A
+:0200EC000DBF46
+:0200ED000DC143
+:0200EE000DC53E
+:0200EF000DCB37
+:0200F0000DCE33
+:0200F1000DD030
+:0200F2000DD728
+:0200F3000DDA24
+:0200F4000DDC21
+:0200F5000DDF1D
+:0200F6000DE417
+:0200F7000DE713
+:0200F8000DE910
+:0200F9000DEC0C
+:0200FA000DEE09
+:0200FB000DF006
+:0200FC000DF500
+:0200FD000DF9FB
+:0200FE000DFCF7
+:0200FF000DFFF3
+:00000001ff

hw/rtl/fp_cores/altera/arria10/acl_fsub.sv

@@ -0,0 +1,68 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_fsub
+// SystemVerilog created on Sun Dec 27 09:47:20 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_fsub (
+    input wire [31:0] a,
+    input wire [31:0] b,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [31:0] fpSubTest_impl_ax0;
+    wire [31:0] fpSubTest_impl_ay0;
+    wire [31:0] fpSubTest_impl_q0;
+    wire fpSubTest_impl_reset0;
+    wire fpSubTest_impl_fpSubTest_impl_ena0;
+
+
+    // fpSubTest_impl(FPCOLUMN,5)@0
+    // out q0@3
+    assign fpSubTest_impl_ax0 = b;
+    assign fpSubTest_impl_ay0 = a;
+    assign fpSubTest_impl_reset0 = areset;
+    assign fpSubTest_impl_fpSubTest_impl_ena0 = en[0];
+    twentynm_fp_mac #(
+        .operation_mode("sp_add"),
+        .adder_subtract("true"),
+        .ax_clock("0"),
+        .ay_clock("0"),
+        .adder_input_clock("0"),
+        .output_clock("0")
+    ) fpSubTest_impl_DSP0 (
+        .aclr({ fpSubTest_impl_reset0, fpSubTest_impl_reset0 }),
+        .clk({1'b0,1'b0,clk}),
+        .ena({ 1'b0, 1'b0, fpSubTest_impl_fpSubTest_impl_ena0 }),
+        .ax(fpSubTest_impl_ax0),
+        .ay(fpSubTest_impl_ay0),
+        .resulta(fpSubTest_impl_q0),
+        .accumulate(),
+        .az(),
+        .chainin(),
+        .chainout()
+    );
+
+    // xOut(GPOUT,4)@3
+    assign q = fpSubTest_impl_q0;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_ftoi.sv

@@ -0,0 +1,508 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_ftoi
+// SystemVerilog created on Sun Dec 27 09:47:21 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_ftoi (
+    input wire [31:0] a,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [0:0] GND_q;
+    wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
+    wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
+    wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
+    wire [7:0] exp_x_uid9_fpToFxPTest_b;
+    wire [22:0] frac_x_uid10_fpToFxPTest_b;
+    wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
+    reg [0:0] excZ_x_uid11_fpToFxPTest_q;
+    wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
+    reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
+    wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi;
+    reg [0:0] fracXIsZero_uid13_fpToFxPTest_q;
+    wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
+    wire [0:0] excI_x_uid15_fpToFxPTest_q;
+    wire [0:0] excN_x_uid16_fpToFxPTest_q;
+    wire [0:0] invExcXZ_uid22_fpToFxPTest_q;
+    wire [23:0] oFracX_uid23_fpToFxPTest_q;
+    wire [0:0] signX_uid25_fpToFxPTest_b;
+    wire [8:0] ovfExpVal_uid26_fpToFxPTest_q;
+    wire [10:0] ovfExpRange_uid27_fpToFxPTest_a;
+    wire [10:0] ovfExpRange_uid27_fpToFxPTest_b;
+    logic [10:0] ovfExpRange_uid27_fpToFxPTest_o;
+    wire [0:0] ovfExpRange_uid27_fpToFxPTest_n;
+    wire [7:0] udfExpVal_uid28_fpToFxPTest_q;
+    wire [10:0] udf_uid29_fpToFxPTest_a;
+    wire [10:0] udf_uid29_fpToFxPTest_b;
+    logic [10:0] udf_uid29_fpToFxPTest_o;
+    wire [0:0] udf_uid29_fpToFxPTest_n;
+    wire [8:0] ovfExpVal_uid30_fpToFxPTest_q;
+    wire [10:0] shiftValE_uid31_fpToFxPTest_a;
+    wire [10:0] shiftValE_uid31_fpToFxPTest_b;
+    logic [10:0] shiftValE_uid31_fpToFxPTest_o;
+    wire [9:0] shiftValE_uid31_fpToFxPTest_q;
+    wire [5:0] shiftValRaw_uid32_fpToFxPTest_in;
+    wire [5:0] shiftValRaw_uid32_fpToFxPTest_b;
+    wire [5:0] maxShiftCst_uid33_fpToFxPTest_q;
+    wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_a;
+    wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_b;
+    logic [11:0] shiftOutOfRange_uid34_fpToFxPTest_o;
+    wire [0:0] shiftOutOfRange_uid34_fpToFxPTest_n;
+    wire [0:0] shiftVal_uid35_fpToFxPTest_s;
+    reg [5:0] shiftVal_uid35_fpToFxPTest_q;
+    wire [31:0] shifterIn_uid37_fpToFxPTest_q;
+    wire [31:0] maxPosValueS_uid39_fpToFxPTest_q;
+    wire [31:0] maxNegValueS_uid40_fpToFxPTest_q;
+    wire [32:0] zRightShiferNoStickyOut_uid41_fpToFxPTest_q;
+    wire [32:0] xXorSignE_uid42_fpToFxPTest_b;
+    wire [32:0] xXorSignE_uid42_fpToFxPTest_q;
+    wire [2:0] d0_uid43_fpToFxPTest_q;
+    wire [33:0] sPostRndFull_uid44_fpToFxPTest_a;
+    wire [33:0] sPostRndFull_uid44_fpToFxPTest_b;
+    logic [33:0] sPostRndFull_uid44_fpToFxPTest_o;
+    wire [33:0] sPostRndFull_uid44_fpToFxPTest_q;
+    wire [32:0] sPostRnd_uid45_fpToFxPTest_in;
+    wire [31:0] sPostRnd_uid45_fpToFxPTest_b;
+    wire [34:0] sPostRnd_uid46_fpToFxPTest_in;
+    wire [33:0] sPostRnd_uid46_fpToFxPTest_b;
+    wire [35:0] rndOvfPos_uid47_fpToFxPTest_a;
+    wire [35:0] rndOvfPos_uid47_fpToFxPTest_b;
+    logic [35:0] rndOvfPos_uid47_fpToFxPTest_o;
+    wire [0:0] rndOvfPos_uid47_fpToFxPTest_c;
+    wire [0:0] ovfPostRnd_uid48_fpToFxPTest_q;
+    wire [2:0] muxSelConc_uid49_fpToFxPTest_q;
+    reg [1:0] muxSel_uid50_fpToFxPTest_q;
+    wire [31:0] maxNegValueU_uid51_fpToFxPTest_q;
+    wire [1:0] finalOut_uid52_fpToFxPTest_s;
+    reg [31:0] finalOut_uid52_fpToFxPTest_q;
+    wire [15:0] rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [15:0] rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [31:0] rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [1:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
+    reg [31:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [27:0] rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [3:0] rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [31:0] rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [23:0] rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [31:0] rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [19:0] rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [11:0] rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [31:0] rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [1:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
+    reg [31:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [30:0] rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [31:0] rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [29:0] rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [1:0] rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [31:0] rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [28:0] rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b;
+    wire [2:0] rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [31:0] rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [1:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s;
+    reg [31:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+    wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b;
+    wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
+    wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
+    reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
+    reg [5:0] redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
+    reg [0:0] redist2_udf_uid29_fpToFxPTest_n_3_q;
+    reg [0:0] redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q;
+    reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
+    reg [0:0] redist5_signX_uid25_fpToFxPTest_b_3_q;
+    reg [0:0] redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
+    reg [0:0] redist7_expXIsMax_uid12_fpToFxPTest_q_3_q;
+    reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_1_q;
+
+
+    // maxNegValueU_uid51_fpToFxPTest(CONSTANT,50)
+    assign maxNegValueU_uid51_fpToFxPTest_q = 32'b00000000000000000000000000000000;
+
+    // maxNegValueS_uid40_fpToFxPTest(CONSTANT,39)
+    assign maxNegValueS_uid40_fpToFxPTest_q = 32'b10000000000000000000000000000000;
+
+    // maxPosValueS_uid39_fpToFxPTest(CONSTANT,38)
+    assign maxPosValueS_uid39_fpToFxPTest_q = 32'b01111111111111111111111111111111;
+
+    // d0_uid43_fpToFxPTest(CONSTANT,42)
+    assign d0_uid43_fpToFxPTest_q = 3'b001;
+
+    // signX_uid25_fpToFxPTest(BITSELECT,24)@0
+    assign signX_uid25_fpToFxPTest_b = a[31:31];
+
+    // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,90)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // GND(CONSTANT,0)
+    assign GND_q = 1'b0;
+
+    // rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80)
+    assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000;
+
+    // rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@1
+    assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3];
+
+    // rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@1
+    assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77)
+    assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00;
+
+    // rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@1
+    assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2];
+
+    // rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@1
+    assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@1
+    assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1];
+
+    // rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@1
+    assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69)
+    assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000;
+
+    // rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@1
+    assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12];
+
+    // rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@1
+    assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
+    assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
+
+    // rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@1
+    assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8];
+
+    // rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@1
+    assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63)
+    assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000;
+
+    // rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@1
+    assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4];
+
+    // rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@1
+    assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56)
+    assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000;
+
+    // rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@1
+    assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16];
+
+    // rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@1
+    assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
+
+    // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
+    assign exp_x_uid9_fpToFxPTest_b = a[30:23];
+
+    // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
+    assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
+    assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
+
+    // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
+    assign frac_x_uid10_fpToFxPTest_b = a[22:0];
+
+    // redist8_frac_x_uid10_fpToFxPTest_b_1(DELAY,94)
+    dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
+    redist8_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
+    assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_1_q};
+
+    // shifterIn_uid37_fpToFxPTest(BITJOIN,36)@1
+    assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q};
+
+    // rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@1
+    assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b;
+    always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
+    begin
+        unique case (rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
+            2'b00 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = shifterIn_uid37_fpToFxPTest_q;
+            2'b01 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+            2'b10 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
+            2'b11 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
+            default : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0;
+        endcase
+    end
+
+    // rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@1
+    assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
+    always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q)
+    begin
+        unique case (rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
+            2'b00 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+            2'b01 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+            2'b10 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+            2'b11 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+            default : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0;
+        endcase
+    end
+
+    // maxShiftCst_uid33_fpToFxPTest(CONSTANT,32)
+    assign maxShiftCst_uid33_fpToFxPTest_q = 6'b100000;
+
+    // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
+    assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101;
+
+    // shiftValE_uid31_fpToFxPTest(SUB,30)@0
+    assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
+    assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    assign shiftValE_uid31_fpToFxPTest_o = $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b);
+    assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0];
+
+    // shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@0
+    assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0];
+    assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0];
+
+    // redist1_shiftValRaw_uid32_fpToFxPTest_b_1(DELAY,87)
+    dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
+    redist1_shiftValRaw_uid32_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid32_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@0 + 1
+    assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q};
+    assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            shiftOutOfRange_uid34_fpToFxPTest_o <= 12'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            shiftOutOfRange_uid34_fpToFxPTest_o <= $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b);
+        end
+    end
+    assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]);
+
+    // shiftVal_uid35_fpToFxPTest(MUX,34)@1
+    assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n;
+    always @(shiftVal_uid35_fpToFxPTest_s or en or redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q or maxShiftCst_uid33_fpToFxPTest_q)
+    begin
+        unique case (shiftVal_uid35_fpToFxPTest_s)
+            1'b0 : shiftVal_uid35_fpToFxPTest_q = redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
+            1'b1 : shiftVal_uid35_fpToFxPTest_q = maxShiftCst_uid33_fpToFxPTest_q;
+            default : shiftVal_uid35_fpToFxPTest_q = 6'b0;
+        endcase
+    end
+
+    // rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@1
+    assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4];
+    assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2];
+    assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0];
+
+    // rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@1 + 1
+    assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s)
+                2'b00 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+                2'b01 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+                2'b10 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+                2'b11 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q;
+                default : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@2
+    assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q};
+
+    // xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@2
+    assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist4_signX_uid25_fpToFxPTest_b_2_q[0]}}, redist4_signX_uid25_fpToFxPTest_b_2_q};
+    assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b;
+
+    // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
+    assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q};
+    assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q};
+    assign sPostRndFull_uid44_fpToFxPTest_o = $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b);
+    assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0];
+
+    // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
+    assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
+    assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
+
+    // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,86)
+    dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
+    redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist5_signX_uid25_fpToFxPTest_b_3(DELAY,91)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist5_signX_uid25_fpToFxPTest_b_3 ( .xin(redist4_signX_uid25_fpToFxPTest_b_2_q), .xout(redist5_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // udfExpVal_uid28_fpToFxPTest(CONSTANT,27)
+    assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101;
+
+    // udf_uid29_fpToFxPTest(COMPARE,28)@0 + 1
+    assign udf_uid29_fpToFxPTest_a = {{3{udfExpVal_uid28_fpToFxPTest_q[7]}}, udfExpVal_uid28_fpToFxPTest_q};
+    assign udf_uid29_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            udf_uid29_fpToFxPTest_o <= 11'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            udf_uid29_fpToFxPTest_o <= $signed(udf_uid29_fpToFxPTest_a) - $signed(udf_uid29_fpToFxPTest_b);
+        end
+    end
+    assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]);
+
+    // redist2_udf_uid29_fpToFxPTest_n_3(DELAY,88)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist2_udf_uid29_fpToFxPTest_n_3 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist2_udf_uid29_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@2
+    assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q};
+    assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1];
+
+    // rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@2 + 1
+    assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q};
+    assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            rndOvfPos_uid47_fpToFxPTest_o <= 36'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            rndOvfPos_uid47_fpToFxPTest_o <= $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b);
+        end
+    end
+    assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35];
+
+    // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25)
+    assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011110;
+
+    // ovfExpRange_uid27_fpToFxPTest(COMPARE,26)@0 + 1
+    assign ovfExpRange_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    assign ovfExpRange_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            ovfExpRange_uid27_fpToFxPTest_o <= 11'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            ovfExpRange_uid27_fpToFxPTest_o <= $signed(ovfExpRange_uid27_fpToFxPTest_a) - $signed(ovfExpRange_uid27_fpToFxPTest_b);
+        end
+    end
+    assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]);
+
+    // redist3_ovfExpRange_uid27_fpToFxPTest_n_3(DELAY,89)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist3_ovfExpRange_uid27_fpToFxPTest_n_3 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
+    assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
+
+    // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
+    assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist6_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,92)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist6_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
+    assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
+
+    // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
+    assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist7_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,93)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist7_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist7_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // excI_x_uid15_fpToFxPTest(LOGICAL,14)@3
+    assign excI_x_uid15_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
+
+    // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3
+    assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q);
+
+    // excN_x_uid16_fpToFxPTest(LOGICAL,15)@3
+    assign excN_x_uid16_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q;
+
+    // ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@3
+    assign ovfPostRnd_uid48_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q | rndOvfPos_uid47_fpToFxPTest_c;
+
+    // muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@3
+    assign muxSelConc_uid49_fpToFxPTest_q = {redist5_signX_uid25_fpToFxPTest_b_3_q, redist2_udf_uid29_fpToFxPTest_n_3_q, ovfPostRnd_uid48_fpToFxPTest_q};
+
+    // muxSel_uid50_fpToFxPTest(LOOKUP,49)@3
+    always @(muxSelConc_uid49_fpToFxPTest_q)
+    begin
+        // Begin reserved scope level
+        unique case (muxSelConc_uid49_fpToFxPTest_q)
+            3'b000 : muxSel_uid50_fpToFxPTest_q = 2'b00;
+            3'b001 : muxSel_uid50_fpToFxPTest_q = 2'b01;
+            3'b010 : muxSel_uid50_fpToFxPTest_q = 2'b11;
+            3'b011 : muxSel_uid50_fpToFxPTest_q = 2'b11;
+            3'b100 : muxSel_uid50_fpToFxPTest_q = 2'b00;
+            3'b101 : muxSel_uid50_fpToFxPTest_q = 2'b10;
+            3'b110 : muxSel_uid50_fpToFxPTest_q = 2'b11;
+            3'b111 : muxSel_uid50_fpToFxPTest_q = 2'b11;
+            default : begin
+                          // unreachable
+                          muxSel_uid50_fpToFxPTest_q = 2'bxx;
+                      end
+        endcase
+        // End reserved scope level
+    end
+
+    // finalOut_uid52_fpToFxPTest(MUX,51)@3
+    assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q;
+    always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
+    begin
+        unique case (finalOut_uid52_fpToFxPTest_s)
+            2'b00 : finalOut_uid52_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
+            2'b01 : finalOut_uid52_fpToFxPTest_q = maxPosValueS_uid39_fpToFxPTest_q;
+            2'b10 : finalOut_uid52_fpToFxPTest_q = maxNegValueS_uid40_fpToFxPTest_q;
+            2'b11 : finalOut_uid52_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q;
+            default : finalOut_uid52_fpToFxPTest_q = 32'b0;
+        endcase
+    end
+
+    // xOut(GPOUT,4)@3
+    assign q = finalOut_uid52_fpToFxPTest_q;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_ftou.sv

@@ -0,0 +1,493 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_ftou
+// SystemVerilog created on Sun Dec 27 09:47:21 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_ftou (
+    input wire [31:0] a,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [0:0] GND_q;
+    wire [0:0] VCC_q;
+    wire [7:0] cstAllOWE_uid6_fpToFxPTest_q;
+    wire [22:0] cstZeroWF_uid7_fpToFxPTest_q;
+    wire [7:0] cstAllZWE_uid8_fpToFxPTest_q;
+    wire [7:0] exp_x_uid9_fpToFxPTest_b;
+    wire [22:0] frac_x_uid10_fpToFxPTest_b;
+    wire [0:0] excZ_x_uid11_fpToFxPTest_qi;
+    reg [0:0] excZ_x_uid11_fpToFxPTest_q;
+    wire [0:0] expXIsMax_uid12_fpToFxPTest_qi;
+    reg [0:0] expXIsMax_uid12_fpToFxPTest_q;
+    wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi;
+    reg [0:0] fracXIsZero_uid13_fpToFxPTest_q;
+    wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q;
+    wire [0:0] excI_x_uid15_fpToFxPTest_q;
+    wire [0:0] excN_x_uid16_fpToFxPTest_q;
+    wire [0:0] invExcXZ_uid22_fpToFxPTest_q;
+    wire [23:0] oFracX_uid23_fpToFxPTest_q;
+    wire [0:0] signX_uid25_fpToFxPTest_b;
+    wire [8:0] ovfExpVal_uid26_fpToFxPTest_q;
+    wire [10:0] ovf_uid27_fpToFxPTest_a;
+    wire [10:0] ovf_uid27_fpToFxPTest_b;
+    logic [10:0] ovf_uid27_fpToFxPTest_o;
+    wire [0:0] ovf_uid27_fpToFxPTest_n;
+    wire [0:0] negOrOvf_uid28_fpToFxPTest_q;
+    wire [7:0] udfExpVal_uid29_fpToFxPTest_q;
+    wire [10:0] udf_uid30_fpToFxPTest_a;
+    wire [10:0] udf_uid30_fpToFxPTest_b;
+    logic [10:0] udf_uid30_fpToFxPTest_o;
+    wire [0:0] udf_uid30_fpToFxPTest_n;
+    wire [8:0] ovfExpVal_uid31_fpToFxPTest_q;
+    wire [10:0] shiftValE_uid32_fpToFxPTest_a;
+    wire [10:0] shiftValE_uid32_fpToFxPTest_b;
+    logic [10:0] shiftValE_uid32_fpToFxPTest_o;
+    wire [9:0] shiftValE_uid32_fpToFxPTest_q;
+    wire [5:0] shiftValRaw_uid33_fpToFxPTest_in;
+    wire [5:0] shiftValRaw_uid33_fpToFxPTest_b;
+    wire [5:0] maxShiftCst_uid34_fpToFxPTest_q;
+    wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_a;
+    wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_b;
+    logic [11:0] shiftOutOfRange_uid35_fpToFxPTest_o;
+    wire [0:0] shiftOutOfRange_uid35_fpToFxPTest_n;
+    wire [0:0] shiftVal_uid36_fpToFxPTest_s;
+    reg [5:0] shiftVal_uid36_fpToFxPTest_q;
+    wire [8:0] zPadd_uid37_fpToFxPTest_q;
+    wire [32:0] shifterIn_uid38_fpToFxPTest_q;
+    wire [31:0] maxPosValueU_uid40_fpToFxPTest_q;
+    wire [31:0] maxNegValueU_uid41_fpToFxPTest_q;
+    wire [33:0] zRightShiferNoStickyOut_uid43_fpToFxPTest_q;
+    wire [34:0] sPostRndFull_uid44_fpToFxPTest_a;
+    wire [34:0] sPostRndFull_uid44_fpToFxPTest_b;
+    logic [34:0] sPostRndFull_uid44_fpToFxPTest_o;
+    wire [34:0] sPostRndFull_uid44_fpToFxPTest_q;
+    wire [32:0] sPostRnd_uid45_fpToFxPTest_in;
+    wire [31:0] sPostRnd_uid45_fpToFxPTest_b;
+    wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in;
+    wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b;
+    wire [0:0] ovfPostRnd_uid47_fpToFxPTest_q;
+    wire [2:0] muxSelConc_uid48_fpToFxPTest_q;
+    reg [1:0] muxSel_uid49_fpToFxPTest_q;
+    wire [1:0] finalOut_uid51_fpToFxPTest_s;
+    reg [31:0] finalOut_uid51_fpToFxPTest_q;
+    wire [16:0] rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [15:0] rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [0:0] rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [32:0] rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [1:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
+    reg [32:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [28:0] rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [3:0] rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [24:0] rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [32:0] rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [20:0] rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [11:0] rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [1:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
+    reg [32:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [31:0] rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [32:0] rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [30:0] rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [1:0] rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [29:0] rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b;
+    wire [2:0] rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [32:0] rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [1:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s;
+    reg [32:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+    wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b;
+    wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
+    wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
+    reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
+    reg [5:0] redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
+    reg [0:0] redist2_udf_uid30_fpToFxPTest_n_2_q;
+    reg [0:0] redist3_ovf_uid27_fpToFxPTest_n_2_q;
+    reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
+    reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_2_q;
+    reg [22:0] redist6_frac_x_uid10_fpToFxPTest_b_1_q;
+
+
+    // maxNegValueU_uid41_fpToFxPTest(CONSTANT,40)
+    assign maxNegValueU_uid41_fpToFxPTest_q = 32'b00000000000000000000000000000000;
+
+    // maxPosValueU_uid40_fpToFxPTest(CONSTANT,39)
+    assign maxPosValueU_uid40_fpToFxPTest_q = 32'b11111111111111111111111111111111;
+
+    // VCC(CONSTANT,1)
+    assign VCC_q = 1'b1;
+
+    // GND(CONSTANT,0)
+    assign GND_q = 1'b0;
+
+    // rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81)
+    assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000;
+
+    // rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@1
+    assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3];
+
+    // rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@1
+    assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78)
+    assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00;
+
+    // rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@1
+    assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2];
+
+    // rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@1
+    assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@1
+    assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1];
+
+    // rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@1
+    assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70)
+    assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000;
+
+    // rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@1
+    assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12];
+
+    // rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@1
+    assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
+    assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
+
+    // rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@1
+    assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8];
+
+    // rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@1
+    assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64)
+    assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000;
+
+    // rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@1
+    assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4];
+
+    // rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@1
+    assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60)
+    assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000;
+
+    // rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@1
+    assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32];
+
+    // rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@1
+    assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55)
+    assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000;
+
+    // rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@1
+    assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16];
+
+    // rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@1
+    assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
+
+    // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
+    assign exp_x_uid9_fpToFxPTest_b = a[30:23];
+
+    // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1
+    assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
+    assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
+
+    // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
+    assign frac_x_uid10_fpToFxPTest_b = a[22:0];
+
+    // redist6_frac_x_uid10_fpToFxPTest_b_1(DELAY,93)
+    dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
+    redist6_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist6_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
+    assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist6_frac_x_uid10_fpToFxPTest_b_1_q};
+
+    // zPadd_uid37_fpToFxPTest(CONSTANT,36)
+    assign zPadd_uid37_fpToFxPTest_q = 9'b000000000;
+
+    // shifterIn_uid38_fpToFxPTest(BITJOIN,37)@1
+    assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q};
+
+    // rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@1
+    assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b;
+    always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
+    begin
+        unique case (rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
+            2'b00 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = shifterIn_uid38_fpToFxPTest_q;
+            2'b01 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            2'b10 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            2'b11 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            default : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0;
+        endcase
+    end
+
+    // rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@1
+    assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
+    always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
+    begin
+        unique case (rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
+            2'b00 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            2'b01 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            2'b10 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            2'b11 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+            default : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0;
+        endcase
+    end
+
+    // maxShiftCst_uid34_fpToFxPTest(CONSTANT,33)
+    assign maxShiftCst_uid34_fpToFxPTest_q = 6'b100001;
+
+    // ovfExpVal_uid31_fpToFxPTest(CONSTANT,30)
+    assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110;
+
+    // shiftValE_uid32_fpToFxPTest(SUB,31)@0
+    assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q};
+    assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    assign shiftValE_uid32_fpToFxPTest_o = $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b);
+    assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0];
+
+    // shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@0
+    assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0];
+    assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0];
+
+    // redist1_shiftValRaw_uid33_fpToFxPTest_b_1(DELAY,88)
+    dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
+    redist1_shiftValRaw_uid33_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid33_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@0 + 1
+    assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q};
+    assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            shiftOutOfRange_uid35_fpToFxPTest_o <= 12'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            shiftOutOfRange_uid35_fpToFxPTest_o <= $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b);
+        end
+    end
+    assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]);
+
+    // shiftVal_uid36_fpToFxPTest(MUX,35)@1
+    assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n;
+    always @(shiftVal_uid36_fpToFxPTest_s or en or redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q or maxShiftCst_uid34_fpToFxPTest_q)
+    begin
+        unique case (shiftVal_uid36_fpToFxPTest_s)
+            1'b0 : shiftVal_uid36_fpToFxPTest_q = redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
+            1'b1 : shiftVal_uid36_fpToFxPTest_q = maxShiftCst_uid34_fpToFxPTest_q;
+            default : shiftVal_uid36_fpToFxPTest_q = 6'b0;
+        endcase
+    end
+
+    // rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@1
+    assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4];
+    assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2];
+    assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0];
+
+    // rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@1 + 1
+    assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s)
+                2'b00 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+                2'b01 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+                2'b10 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+                2'b11 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q;
+                default : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0;
+            endcase
+        end
+    end
+
+    // zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@2
+    assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q};
+
+    // sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
+    assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q};
+    assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q};
+    assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b);
+    assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0];
+
+    // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
+    assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
+    assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
+
+    // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,87)
+    dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
+    redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // signX_uid25_fpToFxPTest(BITSELECT,24)@0
+    assign signX_uid25_fpToFxPTest_b = a[31:31];
+
+    // redist4_signX_uid25_fpToFxPTest_b_2(DELAY,91)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // udfExpVal_uid29_fpToFxPTest(CONSTANT,28)
+    assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101;
+
+    // udf_uid30_fpToFxPTest(COMPARE,29)@0 + 1
+    assign udf_uid30_fpToFxPTest_a = {{3{udfExpVal_uid29_fpToFxPTest_q[7]}}, udfExpVal_uid29_fpToFxPTest_q};
+    assign udf_uid30_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            udf_uid30_fpToFxPTest_o <= 11'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            udf_uid30_fpToFxPTest_o <= $signed(udf_uid30_fpToFxPTest_a) - $signed(udf_uid30_fpToFxPTest_b);
+        end
+    end
+    assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]);
+
+    // redist2_udf_uid30_fpToFxPTest_n_2(DELAY,89)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist2_udf_uid30_fpToFxPTest_n_2 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist2_udf_uid30_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@2
+    assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0];
+    assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33];
+
+    // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25)
+    assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011111;
+
+    // ovf_uid27_fpToFxPTest(COMPARE,26)@0 + 1
+    assign ovf_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b};
+    assign ovf_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            ovf_uid27_fpToFxPTest_o <= 11'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            ovf_uid27_fpToFxPTest_o <= $signed(ovf_uid27_fpToFxPTest_a) - $signed(ovf_uid27_fpToFxPTest_b);
+        end
+    end
+    assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]);
+
+    // redist3_ovf_uid27_fpToFxPTest_n_2(DELAY,90)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist3_ovf_uid27_fpToFxPTest_n_2 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist3_ovf_uid27_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@2
+    assign negOrOvf_uid28_fpToFxPTest_q = redist4_signX_uid25_fpToFxPTest_b_2_q | redist3_ovf_uid27_fpToFxPTest_n_2_q;
+
+    // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
+    assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
+
+    // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
+    assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist6_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
+    assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
+
+    // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1
+    assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist5_expXIsMax_uid12_fpToFxPTest_q_2(DELAY,92)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist5_expXIsMax_uid12_fpToFxPTest_q_2 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // excI_x_uid15_fpToFxPTest(LOGICAL,14)@2
+    assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsZero_uid13_fpToFxPTest_q;
+
+    // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@2
+    assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
+
+    // excN_x_uid16_fpToFxPTest(LOGICAL,15)@2
+    assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsNotZero_uid14_fpToFxPTest_q;
+
+    // ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@2
+    assign ovfPostRnd_uid47_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b;
+
+    // muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@2
+    assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_2_q, redist2_udf_uid30_fpToFxPTest_n_2_q, ovfPostRnd_uid47_fpToFxPTest_q};
+
+    // muxSel_uid49_fpToFxPTest(LOOKUP,48)@2 + 1
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            muxSel_uid49_fpToFxPTest_q <= 2'b00;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (muxSelConc_uid48_fpToFxPTest_q)
+                3'b000 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
+                3'b001 : muxSel_uid49_fpToFxPTest_q <= 2'b01;
+                3'b010 : muxSel_uid49_fpToFxPTest_q <= 2'b11;
+                3'b011 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
+                3'b100 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
+                3'b101 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
+                3'b110 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
+                3'b111 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
+                default : begin
+                              // unreachable
+                              muxSel_uid49_fpToFxPTest_q <= 2'bxx;
+                          end
+            endcase
+        end
+    end
+
+    // finalOut_uid51_fpToFxPTest(MUX,50)@3
+    assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q;
+    always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q)
+    begin
+        unique case (finalOut_uid51_fpToFxPTest_s)
+            2'b00 : finalOut_uid51_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
+            2'b01 : finalOut_uid51_fpToFxPTest_q = maxPosValueU_uid40_fpToFxPTest_q;
+            2'b10 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q;
+            2'b11 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q;
+            default : finalOut_uid51_fpToFxPTest_q = 32'b0;
+        endcase
+    end
+
+    // xOut(GPOUT,4)@3
+    assign q = finalOut_uid51_fpToFxPTest_q;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_gen.log

@@ -0,0 +1,296 @@
+starting execution ... 
+build model options ... 
+argc=22
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fadd
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPAdd@
+@latency 3@
+@LUT 0@
+@DSP 2@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method single path@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=22
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fsub
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPSub@
+@latency 3@
+@LUT 0@
+@DSP 2@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method single path@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=22
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fmul
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPMul@
+@latency 3@
+@LUT 0@
+@DSP 2@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method default@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=22
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fmadd
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 4 cycle(s)
+@@start
+@name FPMultAdd@
+@latency 4@
+@LUT 0@
+@DSP 2@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method multadd@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@inPort 2 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=23
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fdiv
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3 
+The pipeline depth of the block is 20 cycle(s)
+@@start
+@name FPDiv@
+@latency 20@
+@LUT 1067@
+@DSP 7@
+@RAMBits 34304@
+@RAMBlockUsage 3@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method polynomial approximation@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=22
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fsqrt
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3 
+The pipeline depth of the block is 15 cycle(s)
+@@start
+@name FPSqrt@
+@latency 15@
+@LUT 518@
+@DSP 5@
+@RAMBits 15872@
+@RAMBlockUsage 3@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method polynomial approximation@
+@inPort 0 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=25
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_ftoi
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPToFXP@
+@latency 3@
+@LUT 327@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method default@
+@inPort 0 fpieee 8 23@
+@outPort 0 fxp 32 0 1@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=25
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_ftou
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPToFXP@
+@latency 3@
+@LUT 287@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method default@
+@inPort 0 fpieee 8 23@
+@outPort 0 fxp 32 0 0@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=25
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_itof
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 7 cycle(s)
+@@start
+@name FXPToFP@
+@latency 7@
+@LUT 397@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method default@
+@inPort 0 fxp 32 0 1@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=25
+Generation context:
+        Will not generate valid and channel signals 
+    HardFP is enabled enabling set to true 
+    Correct rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_utof
+    Frequency 300MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 7 cycle(s)
+@@start
+@name FXPToFP@
+@latency 7@
+@LUT 363@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 0.50@
+@rounding RNE@
+@method default@
+@inPort 0 fxp 32 0 0@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end

hw/rtl/fp_cores/altera/arria10/acl_gen.sh

@@ -0,0 +1,33 @@
+#!/bin/bash
+
+FAMILY=Arria10
+PREFIX=acl
+
+CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
+
+OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2"
+
+export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
+
+CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
+
+EXP_BITS=8
+MAN_BITS=23
+
+FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
+
+echo Generating IP cores for $FBITS
+{
+    $CMD -name "$PREFIX"_fadd  -frequency 250 FPAdd   $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_fsub  -frequency 250 FPSub   $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_fmul  -frequency 250 FPMul   $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_fmadd -frequency 250 FPMultAdd $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_fdiv  -frequency 250 FPDiv   $EXP_BITS $MAN_BITS 0
+    $CMD -name "$PREFIX"_fsqrt -frequency 250 FPSqrt  $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_ftoi  -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
+    $CMD -name "$PREFIX"_ftou  -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
+    $CMD -name "$PREFIX"_itof  -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
+    $CMD -name "$PREFIX"_utof  -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
+} > acl_gen.log 2>&1
+
+#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .

hw/rtl/fp_cores/altera/arria10/acl_itof.sv

@@ -0,0 +1,520 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_itof
+// SystemVerilog created on Sun Dec 27 09:47:21 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_itof (
+    input wire [31:0] a,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [0:0] GND_q;
+    wire [0:0] signX_uid6_fxpToFPTest_b;
+    wire [31:0] xXorSign_uid7_fxpToFPTest_b;
+    wire [31:0] xXorSign_uid7_fxpToFPTest_qi;
+    reg [31:0] xXorSign_uid7_fxpToFPTest_q;
+    wire [32:0] yE_uid8_fxpToFPTest_a;
+    wire [32:0] yE_uid8_fxpToFPTest_b;
+    logic [32:0] yE_uid8_fxpToFPTest_o;
+    wire [32:0] yE_uid8_fxpToFPTest_q;
+    wire [31:0] y_uid9_fxpToFPTest_in;
+    wire [31:0] y_uid9_fxpToFPTest_b;
+    wire [5:0] maxCount_uid11_fxpToFPTest_q;
+    wire [0:0] inIsZero_uid12_fxpToFPTest_qi;
+    reg [0:0] inIsZero_uid12_fxpToFPTest_q;
+    wire [7:0] msbIn_uid13_fxpToFPTest_q;
+    wire [8:0] expPreRnd_uid14_fxpToFPTest_a;
+    wire [8:0] expPreRnd_uid14_fxpToFPTest_b;
+    logic [8:0] expPreRnd_uid14_fxpToFPTest_o;
+    wire [8:0] expPreRnd_uid14_fxpToFPTest_q;
+    wire [32:0] expFracRnd_uid16_fxpToFPTest_q;
+    wire [0:0] sticky_uid20_fxpToFPTest_qi;
+    reg [0:0] sticky_uid20_fxpToFPTest_q;
+    wire [0:0] nr_uid21_fxpToFPTest_q;
+    wire [0:0] rnd_uid22_fxpToFPTest_q;
+    wire [34:0] expFracR_uid24_fxpToFPTest_a;
+    wire [34:0] expFracR_uid24_fxpToFPTest_b;
+    logic [34:0] expFracR_uid24_fxpToFPTest_o;
+    wire [33:0] expFracR_uid24_fxpToFPTest_q;
+    wire [23:0] fracR_uid25_fxpToFPTest_in;
+    wire [22:0] fracR_uid25_fxpToFPTest_b;
+    wire [9:0] expR_uid26_fxpToFPTest_b;
+    wire [11:0] udf_uid27_fxpToFPTest_a;
+    wire [11:0] udf_uid27_fxpToFPTest_b;
+    logic [11:0] udf_uid27_fxpToFPTest_o;
+    wire [0:0] udf_uid27_fxpToFPTest_n;
+    wire [7:0] expInf_uid28_fxpToFPTest_q;
+    wire [11:0] ovf_uid29_fxpToFPTest_a;
+    wire [11:0] ovf_uid29_fxpToFPTest_b;
+    logic [11:0] ovf_uid29_fxpToFPTest_o;
+    wire [0:0] ovf_uid29_fxpToFPTest_n;
+    wire [0:0] excSelector_uid30_fxpToFPTest_q;
+    wire [22:0] fracZ_uid31_fxpToFPTest_q;
+    wire [0:0] fracRPostExc_uid32_fxpToFPTest_s;
+    reg [22:0] fracRPostExc_uid32_fxpToFPTest_q;
+    wire [0:0] udfOrInZero_uid33_fxpToFPTest_q;
+    wire [1:0] excSelector_uid34_fxpToFPTest_q;
+    wire [7:0] expZ_uid37_fxpToFPTest_q;
+    wire [7:0] expR_uid38_fxpToFPTest_in;
+    wire [7:0] expR_uid38_fxpToFPTest_b;
+    wire [1:0] expRPostExc_uid39_fxpToFPTest_s;
+    reg [7:0] expRPostExc_uid39_fxpToFPTest_q;
+    wire [31:0] outRes_uid40_fxpToFPTest_q;
+    wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi;
+    reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a;
+    wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b;
+    logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o;
+    wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
+    wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s;
+    reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q;
+    wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in;
+    wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b;
+    wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c;
+    wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
+    wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
+    wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
+    wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
+    wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
+    wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
+    wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
+    wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
+    wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b;
+    wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c;
+    wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in;
+    wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
+    wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c;
+    reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q;
+    reg [0:0] redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
+    reg [0:0] redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
+    reg [0:0] redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
+    reg [0:0] redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
+    reg [9:0] redist5_expR_uid26_fxpToFPTest_b_1_q;
+    reg [22:0] redist6_fracR_uid25_fxpToFPTest_b_1_q;
+    reg [0:0] redist7_sticky_uid20_fxpToFPTest_q_2_q;
+    reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
+    reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q;
+    reg [0:0] redist10_signX_uid6_fxpToFPTest_b_1_q;
+    reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q;
+
+
+    // signX_uid6_fxpToFPTest(BITSELECT,5)@0
+    assign signX_uid6_fxpToFPTest_b = a[31:31];
+
+    // redist10_signX_uid6_fxpToFPTest_b_1(DELAY,105)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist10_signX_uid6_fxpToFPTest_b_1 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist10_signX_uid6_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106)
+    dspba_delay_ver #( .width(1), .depth(6), .reset_kind("ASYNC") )
+    redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(redist10_signX_uid6_fxpToFPTest_b_1_q), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expInf_uid28_fxpToFPTest(CONSTANT,27)
+    assign expInf_uid28_fxpToFPTest_q = 8'b11111111;
+
+    // expZ_uid37_fxpToFPTest(CONSTANT,36)
+    assign expZ_uid37_fxpToFPTest_q = 8'b00000000;
+
+    // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@4
+    assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31];
+    assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
+
+    // GND(CONSTANT,0)
+    assign GND_q = 1'b0;
+
+    // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@4
+    assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q};
+
+    // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4
+    assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30];
+    assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0];
+
+    // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67)
+    assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00;
+
+    // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4
+    assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q};
+
+    // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@3
+    assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28];
+    assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0];
+
+    // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60)
+    assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000;
+
+    // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@3
+    assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q};
+
+    // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3
+    assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24];
+    assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0];
+
+    // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3
+    assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q};
+
+    // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2
+    assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16];
+    assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0];
+
+    // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46)
+    assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000;
+
+    // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2
+    assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q};
+
+    // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41)
+    assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000;
+
+    // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + 1
+    assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b};
+    assign xXorSign_uid7_fxpToFPTest_qi = a ^ xXorSign_uid7_fxpToFPTest_b;
+    dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
+    xXorSign_uid7_fxpToFPTest_delay ( .xin(xXorSign_uid7_fxpToFPTest_qi), .xout(xXorSign_uid7_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // yE_uid8_fxpToFPTest(ADD,7)@1
+    assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q};
+    assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, redist10_signX_uid6_fxpToFPTest_b_1_q};
+    assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b);
+    assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0];
+
+    // y_uid9_fxpToFPTest(BITSELECT,8)@1
+    assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0];
+    assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0];
+
+    // redist9_y_uid9_fxpToFPTest_b_1(DELAY,104)
+    dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
+    redist9_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist9_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1
+    assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = y_uid9_fxpToFPTest_b == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2
+    assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist9_y_uid9_fxpToFPTest_b_1_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s)
+            1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist9_y_uid9_fxpToFPTest_b_1_q;
+            1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
+            default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2
+    assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1
+    assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s)
+                1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q;
+                1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q;
+                default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3
+    assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3
+    assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @(vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
+            1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
+            1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
+            default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@3
+    assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@3 + 1
+    assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
+                1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
+                1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
+                default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4
+    assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4
+    assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @(vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
+            1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
+            1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
+            default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@4
+    assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@4
+    assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
+    always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s)
+            1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q;
+            1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q;
+            default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@4
+    assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
+    assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7];
+    assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0];
+
+    // sticky_uid20_fxpToFPTest(LOGICAL,19)@4 + 1
+    assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist7_sticky_uid20_fxpToFPTest_q_2(DELAY,102)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist7_sticky_uid20_fxpToFPTest_q_2 ( .xin(sticky_uid20_fxpToFPTest_q), .xout(redist7_sticky_uid20_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // nr_uid21_fxpToFPTest(LOGICAL,20)@6
+    assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c);
+
+    // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
+    assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
+    assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
+    assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
+
+    // rnd_uid22_fxpToFPTest(LOGICAL,21)@6
+    assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | redist7_sticky_uid20_fxpToFPTest_q_2_q;
+
+    // maxCount_uid11_fxpToFPTest(CONSTANT,10)
+    assign maxCount_uid11_fxpToFPTest_q = 6'b100000;
+
+    // redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@4
+    assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
+
+    // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@4
+    assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q};
+    assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q};
+    assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b);
+    assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7];
+
+    // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@4 + 1
+    assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s)
+                1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q;
+                1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= maxCount_uid11_fxpToFPTest_q;
+                default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0;
+            endcase
+        end
+    end
+
+    // msbIn_uid13_fxpToFPTest(CONSTANT,12)
+    assign msbIn_uid13_fxpToFPTest_q = 8'b10011110;
+
+    // expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1
+    assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q};
+    assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q};
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            expPreRnd_uid14_fxpToFPTest_o <= 9'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
+        end
+    end
+    assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0];
+
+    // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2(DELAY,95)
+    dspba_delay_ver #( .width(24), .depth(2), .reset_kind("ASYNC") )
+    redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6
+    assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q};
+
+    // expFracR_uid24_fxpToFPTest(ADD,23)@6
+    assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q};
+    assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q};
+    assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b);
+    assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0];
+
+    // expR_uid26_fxpToFPTest(BITSELECT,25)@6
+    assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24];
+
+    // redist5_expR_uid26_fxpToFPTest_b_1(DELAY,100)
+    dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") )
+    redist5_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist5_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expR_uid38_fxpToFPTest(BITSELECT,37)@7
+    assign expR_uid38_fxpToFPTest_in = redist5_expR_uid26_fxpToFPTest_b_1_q[7:0];
+    assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0];
+
+    // ovf_uid29_fxpToFPTest(COMPARE,28)@7
+    assign ovf_uid29_fxpToFPTest_a = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
+    assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q};
+    assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b);
+    assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]);
+
+    // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1
+    assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist8_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist8_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // udf_uid27_fxpToFPTest(COMPARE,26)@7
+    assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q};
+    assign udf_uid27_fxpToFPTest_b = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
+    assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b);
+    assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]);
+
+    // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7
+    assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
+
+    // excSelector_uid34_fxpToFPTest(BITJOIN,33)@7
+    assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q};
+
+    // expRPostExc_uid39_fxpToFPTest(MUX,38)@7
+    assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q;
+    always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q)
+    begin
+        unique case (expRPostExc_uid39_fxpToFPTest_s)
+            2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b;
+            2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q;
+            2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
+            2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q;
+            default : expRPostExc_uid39_fxpToFPTest_q = 8'b0;
+        endcase
+    end
+
+    // fracZ_uid31_fxpToFPTest(CONSTANT,30)
+    assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000;
+
+    // fracR_uid25_fxpToFPTest(BITSELECT,24)@6
+    assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0];
+    assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1];
+
+    // redist6_fracR_uid25_fxpToFPTest_b_1(DELAY,101)
+    dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
+    redist6_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist6_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // excSelector_uid30_fxpToFPTest(LOGICAL,29)@7
+    assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
+
+    // fracRPostExc_uid32_fxpToFPTest(MUX,31)@7
+    assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
+    always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist6_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
+    begin
+        unique case (fracRPostExc_uid32_fxpToFPTest_s)
+            1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist6_fracR_uid25_fxpToFPTest_b_1_q;
+            1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q;
+            default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0;
+        endcase
+    end
+
+    // outRes_uid40_fxpToFPTest(BITJOIN,39)@7
+    assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
+
+    // xOut(GPOUT,4)@7
+    assign q = outRes_uid40_fxpToFPTest_q;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/acl_utof.sv

@@ -0,0 +1,486 @@
+// ------------------------------------------------------------------------- 
+// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273)
+// Quartus Prime development tool and MATLAB/Simulink Interface
+// 
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel Corporation's design tools,  logic functions and other
+// software and  tools, and its AMPP partner logic functions, and any output
+// files any  of the foregoing (including  device programming  or simulation
+// files), and  any associated  documentation  or information  are expressly
+// subject  to the terms and  conditions of the  Intel FPGA Software License
+// Agreement, Intel MegaCore Function License Agreement, or other applicable
+// license agreement,  including,  without limitation,  that your use is for
+// the  sole  purpose of  programming  logic devices  manufactured by  Intel
+// and  sold by Intel  or its authorized  distributors. Please refer  to the
+// applicable agreement for further details.
+// ---------------------------------------------------------------------------
+
+// SystemVerilog created from acl_utof
+// SystemVerilog created on Sun Dec 27 09:47:21 2020
+
+
+(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
+module acl_utof (
+    input wire [31:0] a,
+    input wire [0:0] en,
+    output wire [31:0] q,
+    input wire clk,
+    input wire areset
+    );
+
+    wire [0:0] GND_q;
+    wire [5:0] maxCount_uid7_fxpToFPTest_q;
+    wire [0:0] inIsZero_uid8_fxpToFPTest_qi;
+    reg [0:0] inIsZero_uid8_fxpToFPTest_q;
+    wire [7:0] msbIn_uid9_fxpToFPTest_q;
+    wire [8:0] expPreRnd_uid10_fxpToFPTest_a;
+    wire [8:0] expPreRnd_uid10_fxpToFPTest_b;
+    logic [8:0] expPreRnd_uid10_fxpToFPTest_o;
+    wire [8:0] expPreRnd_uid10_fxpToFPTest_q;
+    wire [32:0] expFracRnd_uid12_fxpToFPTest_q;
+    wire [0:0] sticky_uid16_fxpToFPTest_qi;
+    reg [0:0] sticky_uid16_fxpToFPTest_q;
+    wire [0:0] nr_uid17_fxpToFPTest_q;
+    wire [0:0] rnd_uid18_fxpToFPTest_qi;
+    reg [0:0] rnd_uid18_fxpToFPTest_q;
+    wire [34:0] expFracR_uid20_fxpToFPTest_a;
+    wire [34:0] expFracR_uid20_fxpToFPTest_b;
+    logic [34:0] expFracR_uid20_fxpToFPTest_o;
+    wire [33:0] expFracR_uid20_fxpToFPTest_q;
+    wire [23:0] fracR_uid21_fxpToFPTest_in;
+    wire [22:0] fracR_uid21_fxpToFPTest_b;
+    wire [9:0] expR_uid22_fxpToFPTest_b;
+    wire [11:0] udf_uid23_fxpToFPTest_a;
+    wire [11:0] udf_uid23_fxpToFPTest_b;
+    logic [11:0] udf_uid23_fxpToFPTest_o;
+    wire [0:0] udf_uid23_fxpToFPTest_n;
+    wire [7:0] expInf_uid24_fxpToFPTest_q;
+    wire [11:0] ovf_uid25_fxpToFPTest_a;
+    wire [11:0] ovf_uid25_fxpToFPTest_b;
+    logic [11:0] ovf_uid25_fxpToFPTest_o;
+    wire [0:0] ovf_uid25_fxpToFPTest_n;
+    wire [0:0] excSelector_uid26_fxpToFPTest_q;
+    wire [22:0] fracZ_uid27_fxpToFPTest_q;
+    wire [0:0] fracRPostExc_uid28_fxpToFPTest_s;
+    reg [22:0] fracRPostExc_uid28_fxpToFPTest_q;
+    wire [0:0] udfOrInZero_uid29_fxpToFPTest_q;
+    wire [1:0] excSelector_uid30_fxpToFPTest_q;
+    wire [7:0] expZ_uid33_fxpToFPTest_q;
+    wire [7:0] expR_uid34_fxpToFPTest_in;
+    wire [7:0] expR_uid34_fxpToFPTest_b;
+    wire [1:0] expRPostExc_uid35_fxpToFPTest_s;
+    reg [7:0] expRPostExc_uid35_fxpToFPTest_q;
+    wire [31:0] outRes_uid36_fxpToFPTest_q;
+    wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi;
+    reg [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a;
+    wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b;
+    logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o;
+    wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
+    wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s;
+    reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q;
+    wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in;
+    wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b;
+    wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c;
+    wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
+    wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
+    wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
+    wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
+    wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
+    wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
+    wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
+    wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
+    wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b;
+    wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c;
+    wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in;
+    wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b;
+    wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c;
+    reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q;
+    reg [0:0] redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
+    reg [0:0] redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q;
+    reg [0:0] redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q;
+    reg [0:0] redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q;
+    reg [0:0] redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q;
+    reg [9:0] redist6_expR_uid22_fxpToFPTest_b_1_q;
+    reg [22:0] redist7_fracR_uid21_fxpToFPTest_b_1_q;
+    reg [32:0] redist8_expFracRnd_uid12_fxpToFPTest_q_1_q;
+    reg [0:0] redist9_inIsZero_uid8_fxpToFPTest_q_2_q;
+    reg [31:0] redist10_xIn_a_1_q;
+
+
+    // GND(CONSTANT,0)
+    assign GND_q = 1'b0;
+
+    // expInf_uid24_fxpToFPTest(CONSTANT,23)
+    assign expInf_uid24_fxpToFPTest_q = 8'b11111111;
+
+    // expZ_uid33_fxpToFPTest(CONSTANT,32)
+    assign expZ_uid33_fxpToFPTest_q = 8'b00000000;
+
+    // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4
+    assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31];
+    assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
+
+    // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4
+    assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q};
+
+    // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@3
+    assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30];
+    assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0];
+
+    // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63)
+    assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00;
+
+    // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@3
+    assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q};
+
+    // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3
+    assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28];
+    assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0];
+
+    // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56)
+    assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000;
+
+    // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3
+    assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q};
+
+    // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2
+    assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24];
+    assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0];
+
+    // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2
+    assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q};
+
+    // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1
+    assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16];
+    assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0];
+
+    // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42)
+    assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000;
+
+    // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1
+    assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q};
+
+    // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37)
+    assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000;
+
+    // redist10_xIn_a_1(DELAY,101)
+    dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
+    redist10_xIn_a_1 ( .xin(a), .xout(redist10_xIn_a_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + 1
+    assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_delay ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi), .xout(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@1
+    assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @(vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist10_xIn_a_1_q or zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s)
+            1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = redist10_xIn_a_1_q;
+            1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q;
+            default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1
+    assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1
+    assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s)
+                1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q;
+                1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q;
+                default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2
+    assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1
+    assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s)
+                1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q;
+                1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q;
+                default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3
+    assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3
+    assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @(vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s)
+            1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q;
+            1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q;
+            default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@3
+    assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@3 + 1
+    assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s)
+                1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q;
+                1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q;
+                default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0;
+            endcase
+        end
+    end
+
+    // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4
+    assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
+
+    // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4
+    assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q;
+    always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q)
+    begin
+        unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s)
+            1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q;
+            1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q;
+            default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0;
+        endcase
+    end
+
+    // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4
+    assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0];
+    assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7];
+    assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0];
+
+    // sticky_uid16_fxpToFPTest(LOGICAL,15)@4 + 1
+    assign sticky_uid16_fxpToFPTest_qi = fracRnd_uid11_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    sticky_uid16_fxpToFPTest_delay ( .xin(sticky_uid16_fxpToFPTest_qi), .xout(sticky_uid16_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // nr_uid17_fxpToFPTest(LOGICAL,16)@5
+    assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c);
+
+    // maxCount_uid7_fxpToFPTest(CONSTANT,6)
+    assign maxCount_uid7_fxpToFPTest_q = 6'b100000;
+
+    // redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,96)
+    dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
+    redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4 ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,95)
+    dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
+    redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3 ( .xin(vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,94)
+    dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
+    redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2 ( .xin(vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,92)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4
+    assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q};
+
+    // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4
+    assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q};
+    assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q};
+    assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o = $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b);
+    assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7];
+
+    // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@4 + 1
+    assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c;
+    always @ (posedge clk or posedge areset)
+    begin
+        if (areset)
+        begin
+            vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0;
+        end
+        else if (en == 1'b1)
+        begin
+            unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s)
+                1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q;
+                1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= maxCount_uid7_fxpToFPTest_q;
+                default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0;
+            endcase
+        end
+    end
+
+    // msbIn_uid9_fxpToFPTest(CONSTANT,8)
+    assign msbIn_uid9_fxpToFPTest_q = 8'b10011110;
+
+    // expPreRnd_uid10_fxpToFPTest(SUB,9)@5
+    assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q};
+    assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q};
+    assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b);
+    assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0];
+
+    // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91)
+    dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") )
+    redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid11_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5
+    assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q};
+
+    // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5
+    assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0];
+    assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1];
+    assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0];
+
+    // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1
+    assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist8_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,99)
+    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") )
+    redist8_expFracRnd_uid12_fxpToFPTest_q_1 ( .xin(expFracRnd_uid12_fxpToFPTest_q), .xout(redist8_expFracRnd_uid12_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expFracR_uid20_fxpToFPTest(ADD,19)@6
+    assign expFracR_uid20_fxpToFPTest_a = {{2{redist8_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid12_fxpToFPTest_q_1_q};
+    assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q};
+    assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b);
+    assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0];
+
+    // expR_uid22_fxpToFPTest(BITSELECT,21)@6
+    assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24];
+
+    // redist6_expR_uid22_fxpToFPTest_b_1(DELAY,97)
+    dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") )
+    redist6_expR_uid22_fxpToFPTest_b_1 ( .xin(expR_uid22_fxpToFPTest_b), .xout(redist6_expR_uid22_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // expR_uid34_fxpToFPTest(BITSELECT,33)@7
+    assign expR_uid34_fxpToFPTest_in = redist6_expR_uid22_fxpToFPTest_b_1_q[7:0];
+    assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0];
+
+    // ovf_uid25_fxpToFPTest(COMPARE,24)@7
+    assign ovf_uid25_fxpToFPTest_a = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q};
+    assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q};
+    assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b);
+    assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]);
+
+    // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1
+    assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0;
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // redist9_inIsZero_uid8_fxpToFPTest_q_2(DELAY,100)
+    dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
+    redist9_inIsZero_uid8_fxpToFPTest_q_2 ( .xin(inIsZero_uid8_fxpToFPTest_q), .xout(redist9_inIsZero_uid8_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // udf_uid23_fxpToFPTest(COMPARE,22)@7
+    assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q};
+    assign udf_uid23_fxpToFPTest_b = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q};
+    assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b);
+    assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]);
+
+    // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7
+    assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist9_inIsZero_uid8_fxpToFPTest_q_2_q;
+
+    // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7
+    assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q};
+
+    // expRPostExc_uid35_fxpToFPTest(MUX,34)@7
+    assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
+    always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q)
+    begin
+        unique case (expRPostExc_uid35_fxpToFPTest_s)
+            2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b;
+            2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q;
+            2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
+            2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q;
+            default : expRPostExc_uid35_fxpToFPTest_q = 8'b0;
+        endcase
+    end
+
+    // fracZ_uid27_fxpToFPTest(CONSTANT,26)
+    assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000;
+
+    // fracR_uid21_fxpToFPTest(BITSELECT,20)@6
+    assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0];
+    assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1];
+
+    // redist7_fracR_uid21_fxpToFPTest_b_1(DELAY,98)
+    dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
+    redist7_fracR_uid21_fxpToFPTest_b_1 ( .xin(fracR_uid21_fxpToFPTest_b), .xout(redist7_fracR_uid21_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
+
+    // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7
+    assign excSelector_uid26_fxpToFPTest_q = redist9_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n;
+
+    // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7
+    assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q;
+    always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist7_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q)
+    begin
+        unique case (fracRPostExc_uid28_fxpToFPTest_s)
+            1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist7_fracR_uid21_fxpToFPTest_b_1_q;
+            1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q;
+            default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0;
+        endcase
+    end
+
+    // outRes_uid36_fxpToFPTest(BITJOIN,35)@7
+    assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q};
+
+    // xOut(GPOUT,4)@7
+    assign q = outRes_uid36_fxpToFPTest_q;
+
+endmodule

hw/rtl/fp_cores/altera/arria10/dspba_delay_ver.sv

@@ -0,0 +1,95 @@
+// Legal Notice: Copyright 2017 Intel Corporation.  All rights reserved.
+// Your use of  Intel  Corporation's design tools,  logic functions and other
+// software and tools,  and its AMPP  partner logic functions, and  any output
+// files  any of the  foregoing  device programming or simulation files),  and
+// any associated  documentation or information are expressly subject  to  the
+// terms and conditions  of the Intel FPGA Software License Agreement,
+// Intel  MegaCore  Function  License  Agreement, or other applicable license
+// agreement,  including,  without limitation,  that your use  is for the sole
+// purpose of  programming  logic  devices  manufactured by Intel and sold by
+// Intel or its authorized  distributors.  Please  refer  to  the  applicable
+// agreement for further details.
+
+module dspba_delay_ver
+#(
+    parameter width = 8,
+    parameter depth = 1,
+    parameter reset_high = 1'b1,
+    parameter reset_kind = "ASYNC" 
+) (
+    input clk,
+    input aclr,
+    input ena,
+    input [width-1:0] xin,
+    output [width-1:0] xout
+);
+
+    wire reset;
+    reg [width-1:0] delays [depth-1:0];
+
+    assign reset = aclr ^ reset_high;
+    
+    generate
+        if (depth > 0)
+        begin
+            genvar i;
+            for (i = 0; i < depth; ++i)
+            begin : delay_block
+                if (reset_kind == "ASYNC") 
+                begin : sync_reset
+                always @ (posedge clk or negedge reset)
+                    begin: a
+                        if (!reset) begin
+                            delays[i] <= 0;
+                        end else begin
+                            if (ena) begin
+                                if (i > 0) begin
+                                    delays[i] <= delays[i - 1];
+                                end else begin
+                                    delays[i] <= xin;
+                                end
+                            end
+                        end
+                    end
+                end
+
+                if (reset_kind == "SYNC") 
+                begin : async_reset
+                always @ (posedge clk)
+                    begin: a
+                        if (!reset) begin
+                            delays[i] <= 0;
+                        end else begin
+                            if (ena) begin
+                                if (i > 0) begin
+                                    delays[i] <= delays[i - 1];
+                                end else begin
+                                    delays[i] <= xin;
+                                end
+                            end
+                        end
+                    end
+                end
+
+                if (reset_kind == "NONE") 
+                begin : no_reset
+                always @ (posedge clk)
+                    begin: a
+                        if (ena) begin
+                            if (i > 0) begin
+                                delays[i] <= delays[i - 1];
+                            end else begin
+                                delays[i] <= xin;
+                            end
+                        end
+                    end
+                end
+            end
+
+            assign xout = delays[depth - 1];
+        end else begin
+            assign xout = xin;
+        end
+    endgenerate
+    
+endmodule