Initial commit. Harptool, some docs, and the initial logo attempt.
git-svn-id: http://www.cdkersey.com/harp/harptool@1 0246edb2-e076-4747-b392-db732a341fa2
This commit is contained in:
chad
225
src/instruction.cpp
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225
src/instruction.cpp
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/*******************************************************************************
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HARPtools by Chad D. Kersey, Summer 2011
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*******************************************************************************/
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#include <iostream>
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#include <stdlib.h>
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#include "include/instruction.h"
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#include "include/obj.h"
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#include "include/core.h"
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using namespace Harp;
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using namespace std;
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/* It is important that this stays consistent with the Harp::Instruction::Opcode
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enum. */
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const char *Instruction::opStrings[] = {
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"nop", "di", "ei", "tlbadd", "tlbflush", "neg", "not", "and", "or", "xor",
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"add", "sub", "mul", "div", "mod", "shl", "shr","andi",
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"ori", "xori", "addi", "subi", "muli", "divi", "modi", "shli", "shri",
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"jali", "jalr", "jmpi", "jmpr", "clone", "jalis", "jalrs",
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"jmprt", "ld", "st", "ldi", "rtop", "andp", "orp", "xorp", "notp",
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"isneg", "iszero", "halt", "trap", "jmpru", "skep", "reti", "tlbrm", 0
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};
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const bool Instruction::isControlFlow[] = {
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false, false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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true, true, true, true, true, true, true,
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true, false, false, false, false, false, false, false, false,
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false, false, false, false, true, false, true, false
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};
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const bool Instruction::relAddress[] = {
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false, false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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true, false, true, false, false, true, false,
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false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false
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};
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const bool Instruction::allSrcArgs[] = {
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false, false, false, true, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, true, true, false, false, false,
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true, false, true, false, false, false, false, false, false,
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false, false, false, false, true, true, false, false
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};
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const bool Instruction::privileged[] = {
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false, true, true, true, true, false, false, false, false, false,
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false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, false, false, false, false, false,
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false, false, false, false, false, false, false, false, false,
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false, false, true, false, true, true, true, true
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};
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const Instruction::ArgClass Instruction::argClasses[] = {
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AC_NONE, AC_NONE, AC_NONE, AC_3REGSRC, AC_NONE, AC_2REG, AC_2REG, AC_3REG,
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AC_3REG, AC_3REG,
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AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3REG, AC_3IMM,
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AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM, AC_3IMM,
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AC_3IMM,
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AC_2IMM, AC_2REG, AC_1IMM, AC_1REG, AC_1REG, AC_3IMM, AC_3REG,
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AC_1REG, AC_3IMM, AC_3IMMSRC, AC_2IMM, AC_PREG_REG, AC_3PREG, AC_3PREG,
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AC_3PREG, AC_2PREG,
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AC_PREG_REG, AC_PREG_REG, AC_NONE, AC_NONE, AC_1REG, AC_1REG, AC_NONE,
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AC_1REG
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};
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ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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if (inst.predicated) {
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os << "@p" << inst.pred << " ? ";
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}
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os << Instruction::opStrings[inst.op] << ' ';
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if (inst.rdestPresent) os << "%r" << inst.rdest << ' ';
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if (inst.pdestPresent) os << "@p" << inst.pdest << ' ';
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for (int i = 0; i < inst.nRsrc; i++) {
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os << "%r" << inst.rsrc[i] << ' ';
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}
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for (int i = 0; i < inst.nPsrc; i++) {
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os << "@p" << inst.psrc[i] << ' ';
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}
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if (inst.immsrcPresent) {
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if (inst.refLiteral) os << inst.refLiteral->name;
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else os << "#0x" << hex << inst.immsrc;
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}
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os << ';';
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return os;
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}
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void Instruction::executeOn(Core &c) {
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/* If I try to execute a privileged instruction in user mode, throw an
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exception 3. */
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if (privileged[op] && !c.supervisorMode) {
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c.interrupt(3);
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return;
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}
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if (predicated && isControlFlow[op]) {
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bool p0 = c.pred[0][pred];
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for (Size t = 1; t < c.activeThreads; t++) {
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if (c.pred[t][pred] != p0) throw DivergentBranchException();
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}
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}
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Size nextActiveThreads = c.activeThreads;
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for (Size t = 0; t < c.activeThreads; t++) {
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vector<Word> ®(c.reg[t]);
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vector<bool> &pReg(c.pred[t]);
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if (predicated && !pReg[pred]) continue;
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Word memAddr;
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switch (op) {
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case NOP: break;
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case DI: c.interruptEnable = false;
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break;
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case EI: c.interruptEnable = true;
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break;
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case TLBADD: c.mem.tlbAdd(reg[rsrc[0]], reg[rsrc[1]], reg[rsrc[2]]);
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break;
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case TLBFLUSH: c.mem.tlbFlush();
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break;
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case ADD: reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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break;
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case SUB: reg[rdest] = reg[rsrc[0]] - reg[rsrc[1]];
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break;
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case MUL: reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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break;
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case DIV: if (reg[rsrc[1]] == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] / reg[rsrc[1]];
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break;
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case SHL: reg[rdest] = reg[rsrc[0]] << reg[rsrc[1]];
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break;
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case MOD: if (reg[rsrc[1]] == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] % reg[rsrc[1]];
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break;
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case AND: reg[rdest] = reg[rsrc[0]] & reg[rsrc[1]];
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break;
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case NEG: reg[rdest] = -(Word_s)reg[rsrc[0]];
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break;
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case ADDI: reg[rdest] = reg[rsrc[0]] + immsrc;
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break;
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case SUBI: reg[rdest] = reg[rsrc[0]] - immsrc;
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break;
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case MULI: reg[rdest] = reg[rsrc[0]] * immsrc;
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break;
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case DIVI: if (immsrc == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] / immsrc;
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break;
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case MODI: if (immsrc == 0) throw DomainException();
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reg[rdest] = reg[rsrc[0]] % immsrc;
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break;
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case SHRI: reg[rdest] = reg[rsrc[0]] >> immsrc;
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break;
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case SHLI: reg[rdest] = reg[rsrc[0]] << immsrc;
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break;
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case ANDI: reg[rdest] = reg[rsrc[0]] & immsrc;
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break;
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case JMPI: c.pc += immsrc;
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break;
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case JALI: reg[rdest] = c.pc;
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c.pc += immsrc;
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break;
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case JMPR: c.pc = reg[rsrc[0]];
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break;
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case CLONE: c.reg[reg[rsrc[0]]] = reg;
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break;
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case JALIS: nextActiveThreads = reg[rsrc[0]];
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reg[rdest] = c.pc;
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c.pc += immsrc;
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break;
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case JMPRT: nextActiveThreads = 1;
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c.pc = reg[rsrc[0]];
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break;
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case LD: memAddr = reg[rsrc[0]] + immsrc;
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reg[rdest] = c.mem.read(memAddr, c.supervisorMode);
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break;
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case ST: memAddr = reg[rsrc[1]] + immsrc;
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c.mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
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break;
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case LDI: reg[rdest] = immsrc;
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break;
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case RTOP: pReg[pdest] = reg[rsrc[0]];
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break;
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case NOTP: pReg[pdest] = !(pReg[psrc[0]]);
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break;
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case ISNEG: pReg[pdest] = (1ll<<(c.a.getWordSize()*8 - 1))®[rsrc[0]];
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break;
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case HALT: c.activeThreads = 0;
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nextActiveThreads = 0;
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break;
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case TRAP: c.interrupt(0);
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break;
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case JMPRU: c.supervisorMode = false;
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c.pc = reg[rsrc[0]];
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break;
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case SKEP: c.interruptEntry = reg[rsrc[0]];
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break;
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case RETI: if (t == 0) {
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nextActiveThreads = c.shadowActiveThreads;
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c.interruptEnable = c.shadowInterruptEnable;
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c.supervisorMode = c.shadowSupervisorMode;
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reg = c.shadowReg;
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pReg = c.shadowPReg;
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c.pc = c.shadowPc;
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}
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break;
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default:
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cout << "ERROR: Unsupported instruction: " << *this << "\n";
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exit(1);
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}
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if (isControlFlow[op]) break;
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}
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c.activeThreads = nextActiveThreads;
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}
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