Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance

2020-02-22 20:16:13 -05:00
parent b2afe526fe
commit 23aabbf01d
2 changed files with 43 additions and 21 deletions
--- a/rtl/VX_alu.v
+++ b/rtl/VX_alu.v
@@ -14,8 +14,8 @@ module VX_alu(
 	output reg        out_alu_stall
 	);

-		localparam div_pipeline_len = 10;
-		localparam mul_pipeline_len = 3;
+		localparam div_pipeline_len = 20;
+		localparam mul_pipeline_len = 8;

 		wire[31:0] unsigned_div_result;
        wire[31:0] unsigned_rem_result;
@@ -62,6 +62,7 @@ module VX_alu(
 			.WIDTHB(64),
 			.WIDTHP(64),
 			.SPEED("HIGHEST"),
+			.FORCE_LE("YES"),
 			.PIPELINE(mul_pipeline_len)
 		) multiplier (
 			.clock(clk),