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Fixed Single Core with Optimizations

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This commit is contained in:
felsabbagh3
2020-06-28 19:38:36 -07:00
parent 567376971e
commit 21566cdcd7
3 changed files with 9 additions and 8 deletions
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8
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -34,7 +34,7 @@ module VX_cache_core_rsp_merge #(
assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`BANK_BITS-1:0] main_bank_index;
wire grant_valid;
VX_fair_arbiter #(
.N(NUM_BANKS)
) sel_bank (
@@ -42,7 +42,7 @@ module VX_cache_core_rsp_merge #(
.reset (reset),
.requests (per_bank_core_rsp_valid),
.grant_index (main_bank_index),
`UNUSED_PIN (grant_valid),
.grant_valid (grant_valid),
`UNUSED_PIN (grant_onehot)
);
@@ -54,7 +54,7 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
if (grant_valid && per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
@@ -70,7 +70,7 @@ module VX_cache_core_rsp_merge #(
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
if (grant_valid && per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `BANK_BITS'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin