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fix simX build

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This commit is contained in:
Blaise Tine
2020-04-21 01:31:32 -04:00
parent ba4e736782
commit 20ae78f434
31 changed files with 84 additions and 87 deletions
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38
simX/cache_simX.v
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@@ -1,11 +1,11 @@
`include "VX_define.vh"
`include "VX_define.v"
module cache_simX (
input wire clk, // Clock
input wire reset,
// Icache
input wire[31:0] cache_pc_addr,
input wire[31:0] icache_pc_addr,
input wire icache_valid_pc_addr,
output wire icache_stall,
@@ -18,17 +18,17 @@ module cache_simX (
);
//////////////////// ICACHE ///////////////////
VX_icache_request_if VX_icache_req;
assign VX_icache_req.pc_address = cache_pc_addr;
assign VX_icache_req.cache_driver_in_mem_read_o = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.cache_driver_in_mem_write_o = `NO_MEM_WRITE;
assign VX_icache_req.cache_driver_in_valid_o = icache_valid_pc_addr;
assign VX_icache_req.cache_driver_in_data_o = 0;
VX_icache_request_inter VX_icache_req;
assign VX_icache_req.pc_address = icache_pc_addr;
assign VX_icache_req.out_cache_driver_in_mem_read = (icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign VX_icache_req.out_cache_driver_in_valid = icache_valid_pc_addr;
assign VX_icache_req.out_cache_driver_in_data = 0;
VX_icache_rsp_if VX_icache_rsp;
VX_icache_response_inter VX_icache_rsp;
assign icache_stall = VX_icache_rsp.delay;
VX_dram_req_rsp_if #(
VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`ICACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)
@@ -41,22 +41,22 @@ module cache_simX (
//////////////////// DCACHE ///////////////////
VX_dcache_request_if VX_dcache_req;
assign VX_dcache_req.cache_driver_in_mem_read_o = dcache_mem_read;
assign VX_dcache_req.cache_driver_in_mem_write_o = dcache_mem_write;
assign VX_dcache_req.cache_driver_in_data_o = 0;
VX_dcache_request_inter VX_dcache_req;
assign VX_dcache_req.out_cache_driver_in_mem_read = dcache_mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = dcache_mem_write;
assign VX_dcache_req.out_cache_driver_in_data = 0;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
begin
assign VX_dcache_req.cache_driver_in_address_o[curr_t] = dcache_in_addr[curr_t];
assign VX_dcache_req.cache_driver_in_valid_o[curr_t] = dcache_in_valid[curr_t];
assign VX_dcache_req.out_cache_driver_in_address[curr_t] = dcache_in_addr[curr_t];
assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = dcache_in_valid[curr_t];
end
VX_dcache_response_if VX_dcache_rsp;
VX_dcache_response_inter VX_dcache_rsp;
assign dcache_stall = VX_dcache_rsp.delay;
VX_dram_req_rsp_if #(
VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`DCACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)
@@ -66,7 +66,7 @@ module cache_simX (
reg dcache_i_m_ready;
assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
VX_dmem_ctrl dmem_controller (
VX_dmem_controller dmem_ctrl (
.clk (clk),
.reset (reset),
.VX_dram_req_rsp (VX_dram_req_rsp),