minor updates
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2
hw/rtl/cache/VX_miss_resrv.v
vendored
2
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -55,7 +55,7 @@ module VX_miss_resrv #(
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// dequeue
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input wire dequeue
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);
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`USE_FAST_BRAM reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
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reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
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reg [MSHR_SIZE-1:0] valid_table;
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reg [MSHR_SIZE-1:0] ready_table;
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