FIxed first circular issue
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3
rtl/cache/VX_Cache_Bank.v
vendored
3
rtl/cache/VX_Cache_Bank.v
vendored
@@ -46,7 +46,7 @@ module VX_Cache_Bank
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// Inputs
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input wire clk;
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input wire [3:0] state;
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//input wire write_from_mem;
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//input wire write_from_mem;
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// Reading Data
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input wire[$clog2(NUMBER_INDEXES)-1:0] actual_index;
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@@ -118,7 +118,6 @@ module VX_Cache_Bank
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.evict (write_from_mem),
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.data_write(data_write),
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.tag_write (o_tag),
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// Outputs
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.tag_use (tag_use),
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.data_use (data_use),
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