Cleanup before integration
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@@ -4,7 +4,7 @@ module VX_back_end (
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input wire schedule_delay,
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output wire out_mem_delay,
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output wire gpr_stage_delay,
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VX_jal_response_inter VX_jal_rsp,
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VX_branch_response_inter VX_branch_rsp,
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@@ -37,9 +37,6 @@ VX_mem_req_inter VX_exe_mem_req();
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VX_mem_req_inter VX_mem_req();
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VX_gpr_data_inter VX_gpr_data();
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VX_frE_to_bckE_req_inter VX_bckE_req_out();
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// LSU input + output
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VX_lsu_req_inter VX_lsu_req();
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@@ -63,18 +60,14 @@ VX_gpr_stage VX_gpr_stage(
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.schedule_delay (schedule_delay),
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.VX_writeback_inter(VX_writeback_temp),
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.VX_bckE_req (VX_bckE_req),
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.VX_bckE_req_out (VX_bckE_req_out),
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.VX_gpr_data (VX_gpr_data)
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);
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VX_inst_multiplex VX_inst_mult(
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.VX_bckE_req (VX_bckE_req_out),
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.VX_gpr_data (VX_gpr_data),
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// New
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_lsu_req (VX_lsu_req),
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.VX_gpu_inst_req (VX_gpu_inst_req),
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.VX_csr_req (VX_csr_req)
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.VX_csr_req (VX_csr_req),
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// End new
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.memory_delay (out_mem_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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