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Full Evaluation Attempt 1

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This commit is contained in:
felsabbagh3
2019-09-11 01:39:00 -04:00
parent 3c3a443bd5
commit 1b25b10644
14 changed files with 2894 additions and 2945 deletions
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83
rtl/VX_decode.v
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@@ -227,14 +227,17 @@ module VX_decode(
assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE; assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
// UPPER IMMEDIATE // UPPER IMMEDIATE
reg[19:0] temp_upper_immed;
always @(*) begin always @(*) begin
case(curr_opcode) case(curr_opcode)
`LUI_INST: VX_frE_to_bckE_req.upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; `LUI_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
`AUIPC_INST: VX_frE_to_bckE_req.upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3}; `AUIPC_INST: temp_upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
default: VX_frE_to_bckE_req.upper_immed = 20'h0; default: temp_upper_immed = 20'h0;
endcase // curr_opcode endcase // curr_opcode
end end
assign VX_frE_to_bckE_req.upper_immed = temp_upper_immed;
assign jal_b_19_to_12 = in_instruction[19:12]; assign jal_b_19_to_12 = in_instruction[19:12];
assign jal_b_11 = in_instruction[20]; assign jal_b_11 = in_instruction[20];
@@ -256,40 +259,45 @@ module VX_decode(
assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef;
// JAL // JAL
reg temp_jal;
reg[31:0] temp_jal_offset;
always @(*) begin always @(*) begin
case(curr_opcode) case(curr_opcode)
`JAL_INST: `JAL_INST:
begin begin
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0]; temp_jal = 1'b1 && in_valid[0];
VX_frE_to_bckE_req.jal_offset = jal_1_offset; temp_jal_offset = jal_1_offset;
end end
`JALR_INST: `JALR_INST:
begin begin
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0]; temp_jal = 1'b1 && in_valid[0];
VX_frE_to_bckE_req.jal_offset = jal_2_offset; temp_jal_offset = jal_2_offset;
end end
`GPGPU_INST: `GPGPU_INST:
begin begin
if (is_jalrs || is_jmprt) if (is_jalrs || is_jmprt)
begin begin
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0]; temp_jal = 1'b1 && in_valid[0];
VX_frE_to_bckE_req.jal_offset = 32'h0; temp_jal_offset = 32'h0;
end end
end end
`SYS_INST: `SYS_INST:
begin begin
// $display("SYS EBREAK %h", (jal_sys_jal && in_valid[0]) ); // $display("SYS EBREAK %h", (jal_sys_jal && in_valid[0]) );
VX_frE_to_bckE_req.jal = jal_sys_jal && in_valid[0]; temp_jal = jal_sys_jal && in_valid[0];
VX_frE_to_bckE_req.jal_offset = jal_sys_off; temp_jal_offset = jal_sys_off;
end end
default: default:
begin begin
VX_frE_to_bckE_req.jal = 1'b0 && in_valid[0]; temp_jal = 1'b0 && in_valid[0];
VX_frE_to_bckE_req.jal_offset = 32'hdeadbeef; temp_jal_offset = 32'hdeadbeef;
end end
endcase endcase
end end
assign VX_frE_to_bckE_req.jal = temp_jal;
assign VX_frE_to_bckE_req.jal_offset = temp_jal_offset;
wire is_ebreak; wire is_ebreak;
@@ -312,59 +320,66 @@ module VX_decode(
assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
reg[31:0] temp_itype_immed;
always @(*) begin always @(*) begin
case(curr_opcode) case(curr_opcode)
`ALU_INST: VX_frE_to_bckE_req.itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; `ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
`S_INST: VX_frE_to_bckE_req.itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd}; `S_INST: temp_itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd};
`L_INST: VX_frE_to_bckE_req.itype_immed = {{20{u_12[11]}}, u_12}; `L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12};
`B_INST: VX_frE_to_bckE_req.itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; `B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
default: VX_frE_to_bckE_req.itype_immed = 32'hdeadbeef; default: temp_itype_immed = 32'hdeadbeef;
endcase endcase
end end
assign VX_frE_to_bckE_req.itype_immed = temp_itype_immed;
reg[2:0] temp_branch_type;
reg temp_branch_stall;
always @(*) begin always @(*) begin
case(curr_opcode) case(curr_opcode)
`B_INST: `B_INST:
begin begin
out_branch_stall = 1'b1 && in_valid[0]; temp_branch_stall = 1'b1 && in_valid[0];
case(func3) case(func3)
3'h0: VX_frE_to_bckE_req.branch_type = `BEQ; 3'h0: temp_branch_type = `BEQ;
3'h1: VX_frE_to_bckE_req.branch_type = `BNE; 3'h1: temp_branch_type = `BNE;
3'h4: VX_frE_to_bckE_req.branch_type = `BLT; 3'h4: temp_branch_type = `BLT;
3'h5: VX_frE_to_bckE_req.branch_type = `BGT; 3'h5: temp_branch_type = `BGT;
3'h6: VX_frE_to_bckE_req.branch_type = `BLTU; 3'h6: temp_branch_type = `BLTU;
3'h7: VX_frE_to_bckE_req.branch_type = `BGTU; 3'h7: temp_branch_type = `BGTU;
default: VX_frE_to_bckE_req.branch_type = `NO_BRANCH; default: temp_branch_type = `NO_BRANCH;
endcase endcase
end end
`JAL_INST: `JAL_INST:
begin begin
VX_frE_to_bckE_req.branch_type = `NO_BRANCH; temp_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1 && in_valid[0]; temp_branch_stall = 1'b1 && in_valid[0];
end end
`JALR_INST: `JALR_INST:
begin begin
VX_frE_to_bckE_req.branch_type = `NO_BRANCH; temp_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1 && in_valid[0]; temp_branch_stall = 1'b1 && in_valid[0];
end end
`GPGPU_INST: `GPGPU_INST:
begin begin
if (is_jalrs || is_jmprt) if (is_jalrs || is_jmprt)
begin begin
VX_frE_to_bckE_req.branch_type = `NO_BRANCH; temp_branch_type = `NO_BRANCH;
out_branch_stall = 1'b1 && in_valid[0]; temp_branch_stall = 1'b1 && in_valid[0];
end end
end end
default: default:
begin begin
VX_frE_to_bckE_req.branch_type = `NO_BRANCH; temp_branch_type = `NO_BRANCH;
out_branch_stall = 1'b0 && in_valid[0]; temp_branch_stall = 1'b0 && in_valid[0];
end end
endcase endcase
end end
assign VX_frE_to_bckE_req.branch_type = temp_branch_type;
assign out_branch_stall = temp_branch_stall;
always @(*) begin always @(*) begin
// ALU OP // ALU OP

50
rtl/VX_fetch.v
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@@ -65,27 +65,41 @@ module VX_fetch (
wire add_warp = in_wspawn && !in_ebreak && !in_gpr_stall; wire add_warp = in_wspawn && !in_ebreak && !in_gpr_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_gpr_stall; wire remove_warp = in_ebreak && !in_wspawn && !in_gpr_stall;
always @(posedge clk or posedge reset) begin wire[`NW_M1:0] new_warp_state;
if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin wire[`NW_M1:0] new_warp_count;
warp_num <= 0;
end else begin
warp_num <= warp_num + 1;
end
if (add_warp) begin assign new_warp_count = add_warp ? (warp_count + 1) : ((remove_warp ) ? (warp_count - 1) : (warp_count ));
warp_state <= warp_state + 1; assign new_warp_state = add_warp ? (warp_state + 1) : ((remove_warp && (warp_count == 3)) ? (0 ) : ( warp_state ));
warp_count <= warp_count + 1;
// $display("Adding a new warp %h", warp_state+1); wire[`NW_M1:0] new_warp_num ;
end else if (remove_warp) begin // No removing, just invalidating
warp_count <= warp_count - 1; assign new_warp_num = (reset || (warp_num >= warp_state) || remove_warp || add_warp) ? 0 : (warp_num + 1);
// $display("Removing a warp %h %h", in_decode_warp_num, warp_count);
if (warp_count == 2) begin always @(posedge clk or posedge reset) begin
// $display("&&&&&&&&&&&&& STATE 0"); warp_num <= new_warp_num;
warp_state <= 0; warp_state <= new_warp_state;
end warp_count <= new_warp_count;
end
end end
// always @(posedge clk or posedge reset) begin
// if (reset || (warp_num >= warp_state) || remove_warp || add_warp) begin
// warp_num <= 0;
// end else begin
// warp_num <= warp_num + 1;
// end
// if (add_warp) begin
// warp_state <= warp_state + 1;
// warp_count <= warp_count + 1;
// // $display("Adding a new warp %h", warp_state+1);
// end else if (remove_warp) begin // No removing, just invalidating
// warp_count <= warp_count - 1;
// if (warp_count == 2) begin
// warp_state <= 0;
// end
// end
// end
assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak; assign out_ebreak = (in_decode_warp_num == 0) && in_ebreak;

6
rtl/VX_warp.v
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@@ -38,11 +38,11 @@ module VX_warp (
end end
always @(*) begin always @(posedge clk) begin
if (remove) begin if (remove) begin
assign valid = valid_zero; valid <= valid_zero;
end else if (in_change_mask) begin end else if (in_change_mask) begin
assign valid = in_thread_mask; valid <= in_thread_mask;
end end
end end

BIN
rtl/obj_dir/VVortex
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5591
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load Diff

35
rtl/obj_dir/VVortex.h
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@@ -64,13 +64,15 @@ VL_MODULE(VVortex) {
// Begin mtask footprint all: // Begin mtask footprint all:
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0); VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__decode_branch_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__stall,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_state,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_state,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_count,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_count,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__add_warp,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__add_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__remove_warp,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__remove_warp,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_state,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_count,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__new_warp_num,3,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_valid,31,0); VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_glob_valid,31,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_valid_var,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__out_valid_var,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
@@ -114,20 +116,23 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu,4,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jalrs_thread_mask,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jalrs_thread_mask,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jmprt_thread_mask,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__jmprt_thread_mask,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_jal,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_ebreak,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__is_ebreak,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_branch_stall,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_final_alu,4,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__1__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__write_enable,0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__write_enable,0,0);
VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0); VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
};
struct {
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
@@ -157,6 +162,8 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0); VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0); VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__temp_itype_immed,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,1023,0,32); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_a_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,1023,0,32); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__temp_b_reg_data,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data,127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__jal_data,127,0,4);
@@ -185,6 +192,8 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__2__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
};
struct {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__3__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__4__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
@@ -192,8 +201,6 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__5__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__6__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
};
struct {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[32],127,0,4);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4); VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__7__KET____DOT__vx_gpr__DOT__second_ram__DOT__GPR[32],127,0,4);
}; };
@@ -210,7 +217,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid,3,0); VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid,3,0);
VL_SIG8(__Vtableidx1,2,0); VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__warp_num,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0); VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0); VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0); VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
@@ -272,9 +278,9 @@ VL_MODULE(VVortex) {
private: private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp); static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public: public:
static void _combo__TOP__11(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__12(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp); static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp);
private: private:
void _ctor_var_reset() VL_ATTR_COLD; void _ctor_var_reset() VL_ATTR_COLD;
public: public:
@@ -286,14 +292,15 @@ VL_MODULE(VVortex) {
public: public:
static void _eval_initial(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD; static void _eval_initial(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD; static void _eval_settle(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD; static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _multiclk__TOP__10(VVortex__Syms* __restrict vlSymsp); static void _multiclk__TOP__11(VVortex__Syms* __restrict vlSymsp);
static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp); static void _multiclk__TOP__8(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD; static void _settle__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _settle__TOP__9(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128); } VL_ATTR_ALIGNED(128);
#endif // guard #endif // guard

4
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp
View File

@@ -33,8 +33,4 @@ void VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset\n"); );
// Body // Body
csr_address = VL_RAND_RESET_I(12); csr_address = VL_RAND_RESET_I(12);
itype_immed = VL_RAND_RESET_I(32);
branch_type = VL_RAND_RESET_I(3);
jal = VL_RAND_RESET_I(1);
jal_offset = VL_RAND_RESET_I(32);
} }

4
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.h
View File

@@ -18,11 +18,7 @@ VL_MODULE(VVortex_VX_frE_to_bckE_req_inter) {
// LOCAL SIGNALS // LOCAL SIGNALS
// Begin mtask footprint all: // Begin mtask footprint all:
VL_SIG8(branch_type,2,0);
VL_SIG8(jal,0,0);
VL_SIG16(csr_address,11,0); VL_SIG16(csr_address,11,0);
VL_SIG(itype_immed,31,0);
VL_SIG(jal_offset,31,0);
// LOCAL VARIABLES // LOCAL VARIABLES

BIN
rtl/obj_dir/VVortex__ALL.a
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rtl/obj_dir/VVortex__ALLcls.o
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58
rtl/obj_dir/VVortex__verFiles.dat
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@@ -4,17 +4,17 @@ S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/lo
S 2785 897406 1568177864 0 1568177864 0 "VX_alu.v" S 2785 897406 1568177864 0 1568177864 0 "VX_alu.v"
S 2767 897407 1568177864 0 1568177864 0 "VX_back_end.v" S 2767 897407 1568177864 0 1568177864 0 "VX_back_end.v"
S 1836 897410 1568177864 0 1568177864 0 "VX_csr_handler.v" S 1836 897410 1568177864 0 1568177864 0 "VX_csr_handler.v"
S 12015 897411 1568177864 0 1568177864 0 "VX_decode.v" S 12137 897855 1568180188 0 1568180188 0 "VX_decode.v"
S 1676 897412 1568177866 0 1568177866 0 "VX_define.v" S 1676 897412 1568177866 0 1568177866 0 "VX_define.v"
S 3835 897413 1568177866 0 1568177866 0 "VX_execute.v" S 3835 897413 1568177866 0 1568177866 0 "VX_execute.v"
S 5000 897414 1568177866 0 1568177866 0 "VX_fetch.v" S 5559 897862 1568179536 0 1568179536 0 "VX_fetch.v"
S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v" S 6148 897415 1568177866 0 1568177866 0 "VX_forwarding.v"
S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v" S 2701 897416 1568177866 0 1568177866 0 "VX_front_end.v"
S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v" S 399 897417 1568177866 0 1568177866 0 "VX_generic_register.v"
S 1835 897418 1568177866 0 1568177866 0 "VX_gpr.v" S 1835 897418 1568177866 0 1568177866 0 "VX_gpr.v"
S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v" S 5323 897420 1568177866 0 1568177866 0 "VX_gpr_wrapper.v"
S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v" S 2584 897421 1568177866 0 1568177866 0 "VX_memory.v"
S 1903 897425 1568177866 0 1568177866 0 "VX_warp.v" S 1901 899072 1568179744 0 1568179744 0 "VX_warp.v"
S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v" S 1597 897426 1568177868 0 1568177868 0 "VX_writeback.v"
S 4392 897427 1568177868 0 1568177868 0 "Vortex.v" S 4392 897427 1568177868 0 1568177868 0 "Vortex.v"
S 821 897428 1568177868 0 1568177868 0 "byte_enabled_simple_dual_port_ram.v" S 821 897428 1568177868 0 1568177868 0 "byte_enabled_simple_dual_port_ram.v"
@@ -42,32 +42,32 @@ S 557 897450 1568177890 0 1568177890 0 "interfaces
S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v" S 348 897451 1568177890 0 1568177890 0 "interfaces//VX_mw_wb_inter.v"
S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v" S 297 897452 1568177890 0 1568177890 0 "interfaces//VX_warp_ctl_inter.v"
S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v" S 273 897453 1568177890 0 1568177890 0 "interfaces//VX_wb_inter.v"
T 1312387 897481 1568178034 0 1568178034 0 "obj_dir/VVortex.cpp" T 1307652 897708 1568180202 0 1568180202 0 "obj_dir/VVortex.cpp"
T 23516 897479 1568178032 0 1568178032 0 "obj_dir/VVortex.h" T 24070 897706 1568180202 0 1568180202 0 "obj_dir/VVortex.h"
T 1791 897581 1568178034 0 1568178034 0 "obj_dir/VVortex.mk" T 1791 897807 1568180202 0 1568180202 0 "obj_dir/VVortex.mk"
T 914 897569 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.cpp" T 914 897795 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 897568 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_branch_response_inter.h" T 1029 897794 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 897565 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp" T 1210 897791 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 897564 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_request_inter.h" T 1135 897790 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 897563 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp" T 988 897789 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 897562 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_dcache_response_inter.h" T 1045 897788 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1059 897567 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp" T 914 897793 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1142 897566 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h" T 1031 897792 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 897577 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp" T 884 897803 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 897576 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h" T 1008 897802 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 897573 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp" T 865 897799 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 897572 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_inst_meta_inter.h" T 987 897798 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 897575 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.cpp" T 885 897801 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 897574 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_mem_req_inter.h" T 1005 897800 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 897571 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp" T 902 897797 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 897570 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_warp_ctl_inter.h" T 1017 897796 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 825 897579 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.cpp" T 825 897805 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 897578 1568178034 0 1568178034 0 "obj_dir/VVortex_VX_wb_inter.h" T 954 897804 1568180202 0 1568180202 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 897478 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.cpp" T 3499 897705 1568180202 0 1568180202 0 "obj_dir/VVortex__Syms.cpp"
T 1855 897477 1568178032 0 1568178032 0 "obj_dir/VVortex__Syms.h" T 1855 897704 1568180202 0 1568180202 0 "obj_dir/VVortex__Syms.h"
T 2113 897582 1568178034 0 1568178034 0 "obj_dir/VVortex__ver.d" T 2113 897808 1568180202 0 1568180202 0 "obj_dir/VVortex__ver.d"
T 0 0 1568178034 0 1568178034 0 "obj_dir/VVortex__verFiles.dat" T 0 0 1568180202 0 1568180202 0 "obj_dir/VVortex__verFiles.dat"
T 1530 897580 1568178034 0 1568178034 0 "obj_dir/VVortex_classes.mk" T 1530 897806 1568180202 0 1568180202 0 "obj_dir/VVortex_classes.mk"
S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v" S 1884 897454 1568177900 0 1568177900 0 "pipe_regs//VX_d_e_reg.v"
S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v" S 1538 897455 1568177900 0 1568177900 0 "pipe_regs//VX_e_m_reg.v"
S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v" S 751 897456 1568177900 0 1568177900 0 "pipe_regs//VX_f_d_reg.v"

BIN
rtl/obj_dir/test_bench.o
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6
rtl/quartus/Makefile
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@@ -1,6 +1,6 @@
PROJECT = VX_gpr_syn PROJECT = Vortex
TOP_LEVEL_ENTITY = VX_gpr_syn TOP_LEVEL_ENTITY = Vortex
SRC_FILE = VX_gpr_syn.v SRC_FILE = Vortex.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family # Part, Family

2
rtl/results.txt
View File

@@ -3,5 +3,5 @@
# of forwarding stalls: 0 # of forwarding stalls: 0
# of branch stalls: 0 # of branch stalls: 0
# CPI: 1.00015 # CPI: 1.00015
# time to simulate: 2.18298e-314 milliseconds # time to simulate: 2.15924e-314 milliseconds
# GRADE: Failed on test: 4294967295 # GRADE: Failed on test: 4294967295