Less expensive but slower fetch logic
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@@ -3,7 +3,9 @@
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module VX_memory (
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/* verilator lint_off UNUSED */
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input wire clk,
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/* verilator lint_on UNUSED */
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input wire[31:0] in_alu_result[`NT_M1:0],
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input wire[2:0] in_mem_read,
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input wire[2:0] in_mem_write,
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@@ -43,11 +45,11 @@ module VX_memory (
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// end
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// end
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wire[15:0] addr_0 = in_alu_result[0][31:16];
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// wire[15:0] addr_0 = in_alu_result[0][31:16];
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wire sm_valid[`NT_M1:0];
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// wire sm_valid[`NT_M1:0];
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assign sm_valid = (addr_0 != 16'hFFFF) ? in_valid : in_valid;
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// assign sm_valid = (addr_0 != 16'hFFFF) ? in_valid : in_valid;
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// wire z_valid[`NT_M1:0];
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@@ -63,21 +65,22 @@ module VX_memory (
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wire[31:0] sm_out_data[`NT_M1:0];
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// wire[31:0] sm_out_data[`NT_M1:0];
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VX_shared_memory vx_shared_memory(
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.clk (clk),
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.in_address (in_alu_result),
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.in_mem_read (in_mem_read),
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.in_mem_write(in_mem_write),
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.in_valid (sm_valid),
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.in_data (in_rd2),
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.out_data (sm_out_data)
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);
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// VX_shared_memory vx_shared_memory(
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// .clk (clk),
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// .in_address (in_alu_result),
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// .in_mem_read (in_mem_read),
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// .in_mem_write(in_mem_write),
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// .in_valid (sm_valid),
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// .in_data (in_rd2),
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// .out_data (sm_out_data)
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// );
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assign out_mem_result = sm_valid ? sm_out_data : in_cache_driver_out_data;
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// assign out_mem_result = sm_valid ? sm_out_data : in_cache_driver_out_data;
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assign out_mem_result = in_cache_driver_out_data;
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assign out_alu_result = in_alu_result;
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assign out_rd = in_rd;
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assign out_wb = in_wb;
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