fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
This commit is contained in:
Blaise Tine
@@ -13,6 +13,7 @@ struct params_t {
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uint32_t sets_per_bank;
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uint32_t blocks_per_set;
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uint32_t words_per_block;
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uint32_t log2_num_inputs;
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uint32_t word_select_addr_start;
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uint32_t word_select_addr_end;
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@@ -31,8 +32,10 @@ struct params_t {
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uint32_t offset_bits = config.B - config.W;
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uint32_t log2_bank_size = config.C - bank_bits;
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uint32_t index_bits = log2_bank_size - (config.B << config.A);
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assert(log2_bank_size >= config.B);
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assert(log2_bank_size >= config.B);
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this->log2_num_inputs = log2ceil(config.num_inputs);
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this->words_per_block = 1 << offset_bits;
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this->blocks_per_set = 1 << config.A;
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this->sets_per_bank = 1 << index_bits;
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@@ -104,7 +107,7 @@ struct set_t {
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struct bank_req_info_t {
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bool valid;
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uint32_t req_id;
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uint32_t req_tag;
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uint64_t req_tag;
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};
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struct bank_req_t {
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@@ -194,7 +197,7 @@ public:
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return root_entry;
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}
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bool try_pop(bank_req_t* out) {
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bool pop(bank_req_t* out) {
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for (auto& entry : entries_) {
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if (entry.valid && entry.mshr_replay) {
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*out = entry;
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@@ -208,16 +211,13 @@ public:
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};
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struct bank_t {
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std::vector<set_t> sets;
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MSHR mshr;
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std::queue<bank_req_t> stall_buffer;
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bank_req_t active_req;
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std::vector<set_t> sets;
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MSHR mshr;
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bank_t(const CacheConfig& config,
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const params_t& params)
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: sets(params.sets_per_bank, params.blocks_per_set)
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, mshr(config.mshr_size)
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, active_req(config.ports_per_bank)
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{}
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};
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@@ -229,8 +229,8 @@ private:
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CacheConfig config_;
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params_t params_;
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std::vector<bank_t> banks_;
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std::vector<std::queue<uint32_t>> core_rsps_;
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Switch<MemReq, MemRsp>::Ptr mem_switch_;
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Switch<MemReq, MemRsp>::Ptr mem_switch_;
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Switch<MemReq, MemRsp>::Ptr bypass_switch_;
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std::vector<MasterPort<MemReq>> mem_req_ports_;
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std::vector<SlavePort<MemRsp>> mem_rsp_ports_;
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@@ -240,241 +240,270 @@ public:
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, config_(config)
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, params_(config)
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, banks_(config.num_banks, {config, params_})
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, core_rsps_(config.num_inputs)
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, mem_req_ports_(config.num_banks, simobject)
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, mem_rsp_ports_(config.num_banks, simobject)
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{
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bypass_switch_ = Switch<MemReq, MemRsp>::Create("bypass_arb", ArbiterType::Priority, 2);
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bypass_switch_->ReqOut.bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&bypass_switch_->RspIn);
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if (config.num_banks > 1) {
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mem_switch_ = Switch<MemReq, MemRsp>::Create("mem_arb", ArbiterType::RoundRobin, config.num_banks);
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for (uint32_t i = 0, n = config.num_banks; i < n; ++i) {
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mem_req_ports_.at(i).bind(&mem_switch_->ReqIn.at(i));
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mem_switch_->RspOut.at(i).bind(&mem_rsp_ports_.at(i));
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}
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mem_switch_->ReqOut.bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&mem_switch_->RspIn);
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mem_switch_->ReqOut.bind(&bypass_switch_->ReqIn.at(0));
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bypass_switch_->RspOut.at(0).bind(&mem_switch_->RspIn);
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} else {
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mem_req_ports_.at(0).bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&mem_rsp_ports_.at(0));
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mem_req_ports_.at(0).bind(&bypass_switch_->ReqIn.at(0));
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bypass_switch_->RspOut.at(0).bind(&mem_rsp_ports_.at(0));
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}
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}
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void step(uint64_t /*cycle*/) {
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// process core response
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for (uint32_t req_id = 0, n = config_.num_inputs; req_id < n; ++req_id) {
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auto& core_rsp = core_rsps_.at(req_id);
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if (!core_rsp.empty()) {
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simobject_->CoreRspPorts.at(req_id).send(MemRsp{core_rsp.front()}, config_.latency);
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core_rsp.pop();
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}
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// handle bypasss responses
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auto& bypass_port = bypass_switch_->RspOut.at(1);
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if (!bypass_port.empty()) {
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auto& mem_rsp = bypass_port.top();
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uint32_t req_id = mem_rsp.tag & ((1 << params_.log2_num_inputs)-1);
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uint64_t tag = mem_rsp.tag >> params_.log2_num_inputs;
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MemRsp core_rsp(tag);
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simobject_->CoreRspPorts.at(req_id).send(core_rsp, config_.latency);
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bypass_port.pop();
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}
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for (auto& bank : banks_) {
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auto& active_req = bank.active_req;
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std::vector<bank_req_t> pipeline_reqs(config_.num_banks, config_.ports_per_bank);
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// try chedule mshr replay
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if (!active_req.valid) {
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bank.mshr.try_pop(&active_req);
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}
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// try schedule stall queue if MSHR has space
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if (!active_req.valid
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&& !bank.stall_buffer.empty()
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&& !bank.mshr.full()) {
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active_req = bank.stall_buffer.front();
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bank.stall_buffer.pop();
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}
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}
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// handle MSHR replay
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for (uint32_t bank_id = 0, n = config_.num_banks; bank_id < n; ++bank_id) {
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auto& bank = banks_.at(bank_id);
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auto& pipeline_req = pipeline_reqs.at(bank_id);
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bank.mshr.pop(&pipeline_req);
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}
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// handle memory fills
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for (uint32_t i = 0, n = config_.num_banks; i < n; ++i) {
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MemRsp mem_rsp;
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if (mem_rsp_ports_.at(i).read(&mem_rsp)) {
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this->processMemoryFill(i, mem_rsp.tag);
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std::vector<bool> pending_fill_req(config_.num_banks, false);
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for (uint32_t bank_id = 0, n = config_.num_banks; bank_id < n; ++bank_id) {
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auto& mem_rsp_port = mem_rsp_ports_.at(bank_id);
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if (!mem_rsp_port.empty()) {
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auto& mem_rsp = mem_rsp_port.top();
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this->processMemoryFill(bank_id, mem_rsp.tag);
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pending_fill_req.at(bank_id) = true;
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mem_rsp_port.pop();
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}
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}
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// handle incoming core requests
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for (uint32_t i = 0, n = config_.num_inputs; i < n; ++i) {
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MemReq core_req;
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if (!simobject_->CoreReqPorts.at(i).read(&core_req))
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for (uint32_t req_id = 0, n = config_.num_inputs; req_id < n; ++req_id) {
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auto& core_req_port = simobject_->CoreReqPorts.at(req_id);
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if (core_req_port.empty())
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continue;
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auto bank_id = params_.addr_bank_id(core_req.addr);
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auto set_id = params_.addr_set_id(core_req.addr);
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auto tag = params_.addr_tag(core_req.addr);
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auto port_id = i % config_.ports_per_bank;
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auto& core_req = core_req_port.top();
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// check cache bypassing
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if (core_req.is_io) {
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// send IO request
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this->processIORequest(core_req, req_id);
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// remove request
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core_req_port.pop();
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continue;
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}
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auto bank_id = params_.addr_bank_id(core_req.addr);
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auto set_id = params_.addr_set_id(core_req.addr);
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auto tag = params_.addr_tag(core_req.addr);
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auto port_id = req_id % config_.ports_per_bank;
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// create abnk request
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// create bank request
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bank_req_t bank_req(config_.ports_per_bank);
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bank_req.valid = true;
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bank_req.write = core_req.write;
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bank_req.mshr_replay = false;
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bank_req.tag = tag;
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bank_req.set_id = set_id;
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bank_req.infos.at(port_id) = {true, i, core_req.tag};
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bank_req.infos.at(port_id) = {true, req_id, core_req.tag};
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auto& bank = banks_.at(bank_id);
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// check MSHR capacity
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if (bank.mshr.full()) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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auto& bank = banks_.at(bank_id);
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auto& pipeline_req = pipeline_reqs.at(bank_id);
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// check pending MSHR replay
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if (pipeline_req.valid
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&& pipeline_req.mshr_replay) {
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// stall
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continue;
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}
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// check pending fill request
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if (pending_fill_req.at(bank_id)) {
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// stall
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continue;
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}
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auto& active_req = bank.active_req;
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// check pending MSHR request
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if (active_req.valid
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&& active_req.mshr_replay) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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// check MSHR capacity if read or writeback
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if ((!core_req.write || !config_.write_through)
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&& bank.mshr.full()) {
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// stall
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continue;
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}
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}
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// check bank conflicts
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if (active_req.valid) {
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if (pipeline_req.valid) {
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// check port conflict
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if (active_req.write != core_req.write
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|| active_req.set_id != set_id
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|| active_req.tag != tag
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|| active_req.infos[port_id].valid) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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if (pipeline_req.write != core_req.write
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|| pipeline_req.set_id != set_id
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|| pipeline_req.tag != tag
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|| pipeline_req.infos[port_id].valid) {
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// stall
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continue;
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}
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// update pending request infos
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active_req.infos[port_id] = bank_req.infos[port_id];
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pipeline_req.infos[port_id] = bank_req.infos[port_id];
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} else {
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// schedule new request
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active_req = bank_req;
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pipeline_req = bank_req;
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}
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// remove request
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core_req_port.pop();
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}
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// process active request
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for (uint32_t bank_id = 0, n = config_.num_banks; bank_id < n; ++bank_id) {
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this->processBankRequest(bank_id);
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// process active request
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this->processBankRequest(pipeline_reqs);
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}
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void processIORequest(const MemReq& core_req, uint32_t req_id) {
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{
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MemReq mem_req(core_req);
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mem_req.tag = (core_req.tag << params_.log2_num_inputs) + req_id;
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bypass_switch_->ReqIn.at(1).send(mem_req, 1);
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}
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if (core_req.write && config_.write_reponse) {
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simobject_->CoreRspPorts.at(req_id).send(MemRsp{core_req.tag}, 1);
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}
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}
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void processMemoryFill(uint32_t bank_id, uint32_t mshr_id) {
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// update block
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auto& bank = banks_.at(bank_id);
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auto& root_entry = bank.mshr.replay(mshr_id);
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auto& set = bank.sets.at(root_entry.set_id);
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auto& block = set.blocks.at(root_entry.block_id);
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auto& bank = banks_.at(bank_id);
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auto& entry = bank.mshr.replay(mshr_id);
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auto& set = bank.sets.at(entry.set_id);
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auto& block = set.blocks.at(entry.block_id);
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block.valid = true;
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block.tag = root_entry.tag;
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block.tag = entry.tag;
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}
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void processBankRequest(uint32_t bank_id) {
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auto& bank = banks_.at(bank_id);
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auto& active_req = bank.active_req;
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if (!active_req.valid)
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return;
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void processBankRequest(const std::vector<bank_req_t>& pipeline_reqs) {
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for (uint32_t bank_id = 0, n = config_.num_banks; bank_id < n; ++bank_id) {
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auto& pipeline_req = pipeline_reqs.at(bank_id);
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if (!pipeline_req.valid)
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continue;
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active_req.valid = false;
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auto& bank = banks_.at(bank_id);
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auto& set = bank.sets.at(pipeline_req.set_id);
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auto& set = bank.sets.at(active_req.set_id);
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if (active_req.mshr_replay) {
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// send core response
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for (auto& info : active_req.infos) {
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core_rsps_.at(info.req_id).emplace(info.req_tag);
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}
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} else {
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bool hit = false;
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bool found_free_block = false;
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int hit_block_id = 0;
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int repl_block_id = 0;
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uint32_t max_cnt = 0;
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for (int i = 0, n = set.blocks.size(); i < n; ++i) {
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auto& block = set.blocks.at(i);
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if (block.valid) {
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if (block.tag == active_req.tag) {
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block.lru_ctr = 0;
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hit_block_id = i;
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hit = true;
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} else {
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++block.lru_ctr;
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}
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if (max_cnt < block.lru_ctr) {
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max_cnt = block.lru_ctr;
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if (pipeline_req.mshr_replay) {
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// send core response
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for (auto& info : pipeline_req.infos) {
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simobject_->CoreRspPorts.at(info.req_id).send(MemRsp{info.req_tag}, config_.latency);
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}
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} else {
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bool hit = false;
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bool found_free_block = false;
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int hit_block_id = 0;
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int repl_block_id = 0;
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uint32_t max_cnt = 0;
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for (int i = 0, n = set.blocks.size(); i < n; ++i) {
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auto& block = set.blocks.at(i);
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if (block.valid) {
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if (block.tag == pipeline_req.tag) {
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block.lru_ctr = 0;
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hit_block_id = i;
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hit = true;
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} else {
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++block.lru_ctr;
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}
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if (max_cnt < block.lru_ctr) {
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max_cnt = block.lru_ctr;
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repl_block_id = i;
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}
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} else {
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found_free_block = true;
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repl_block_id = i;
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}
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} else {
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found_free_block = true;
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repl_block_id = i;
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}
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}
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if (hit) {
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//
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// MISS handling
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//
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if (active_req.write) {
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// handle write hit
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auto& hit_block = set.blocks.at(hit_block_id);
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if (config_.write_through) {
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// forward write request to memory
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, hit_block.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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} else {
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// mark block as dirty
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hit_block.dirty = true;
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}
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}
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// send core response
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for (auto& info : active_req.infos) {
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core_rsps_.at(info.req_id).emplace(info.req_tag);
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}
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} else {
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//
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// MISS handling
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//
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if (!found_free_block && !config_.write_through) {
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// write back dirty block
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auto& repl_block = set.blocks.at(repl_block_id);
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if (repl_block.dirty) {
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, repl_block.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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}
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}
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if (active_req.write && config_.write_through) {
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// forward write request to memory
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{
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, active_req.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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if (hit) {
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//
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// MISS handling
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//
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if (pipeline_req.write) {
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// handle write hit
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auto& hit_block = set.blocks.at(hit_block_id);
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if (config_.write_through) {
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// forward write request to memory
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, pipeline_req.set_id, hit_block.tag);
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mem_req.write = true;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
|
||||
} else {
|
||||
// mark block as dirty
|
||||
hit_block.dirty = true;
|
||||
}
|
||||
}
|
||||
// send core response
|
||||
for (auto& info : active_req.infos) {
|
||||
core_rsps_.at(info.req_id).emplace(info.req_tag);
|
||||
if (!pipeline_req.write || config_.write_reponse) {
|
||||
for (auto& info : pipeline_req.infos) {
|
||||
simobject_->CoreRspPorts.at(info.req_id).send(MemRsp{info.req_tag}, config_.latency);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
//
|
||||
// MISS handling
|
||||
//
|
||||
if (!found_free_block && !config_.write_through) {
|
||||
// write back dirty block
|
||||
auto& repl_block = set.blocks.at(repl_block_id);
|
||||
if (repl_block.dirty) {
|
||||
MemReq mem_req;
|
||||
mem_req.addr = params_.mem_addr(bank_id, pipeline_req.set_id, repl_block.tag);
|
||||
mem_req.write = true;
|
||||
mem_req_ports_.at(bank_id).send(mem_req, 1);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// lookup
|
||||
int pending = bank.mshr.lookup(active_req);
|
||||
|
||||
// allocate MSHR
|
||||
int mshr_id = bank.mshr.allocate(active_req, repl_block_id);
|
||||
|
||||
// send fill request
|
||||
if (pending == -1) {
|
||||
MemReq mem_req;
|
||||
mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, active_req.tag);
|
||||
mem_req.write = active_req.write;
|
||||
mem_req.tag = mshr_id;
|
||||
mem_req_ports_.at(bank_id).send(mem_req, 1);
|
||||
if (pipeline_req.write && config_.write_through) {
|
||||
// forward write request to memory
|
||||
{
|
||||
MemReq mem_req;
|
||||
mem_req.addr = params_.mem_addr(bank_id, pipeline_req.set_id, pipeline_req.tag);
|
||||
mem_req.write = true;
|
||||
mem_req_ports_.at(bank_id).send(mem_req, 1);
|
||||
}
|
||||
// send core response
|
||||
if (config_.write_reponse) {
|
||||
for (auto& info : pipeline_req.infos) {
|
||||
simobject_->CoreRspPorts.at(info.req_id).send(MemRsp{info.req_tag}, config_.latency);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// MSHR lookup
|
||||
int pending = bank.mshr.lookup(pipeline_req);
|
||||
|
||||
// allocate MSHR
|
||||
int mshr_id = bank.mshr.allocate(pipeline_req, repl_block_id);
|
||||
|
||||
// send fill request
|
||||
if (pending == -1) {
|
||||
MemReq mem_req;
|
||||
mem_req.addr = params_.mem_addr(bank_id, pipeline_req.set_id, pipeline_req.tag);
|
||||
mem_req.write = pipeline_req.write;
|
||||
mem_req.tag = mshr_id;
|
||||
mem_req_ports_.at(bank_id).send(mem_req, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user