L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

hw/rtl/interfaces/VX_lsu_req_if.v

@@ -10,14 +10,11 @@ interface VX_lsu_req_if ();
     wire [`NW_BITS-1:0]             wid;
     wire [`NUM_THREADS-1:0]         tmask;    
     wire [31:0]                     PC;
-
     wire                            rw; 
     wire [`BYTEEN_BITS-1:0]         byteen;
-
     wire [`NUM_THREADS-1:0][31:0]   store_data;
     wire [`NUM_THREADS-1:0][31:0]   base_addr;    
-    wire [31:0]                     offset;   
-
+    wire [31:0]                     offset;
     wire [`NR_BITS-1:0]             rd;
     wire                            wb;