L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
--- a/hw/rtl/cache/VX_cache_miss_resrv.v
+++ b/hw/rtl/cache/VX_cache_miss_resrv.v
@@ -17,7 +17,7 @@ module VX_cache_miss_resrv #(
    // core request tag size
    parameter CORE_TAG_WIDTH                = 1,
    // Snooping request tag width
-    parameter SNP_REQ_TAG_WIDTH             = 1,
+    parameter SNP_TAG_WIDTH                 = 1,
    // size of tag id in core request tag
    parameter CORE_TAG_ID_BITS              = 0    
 ) (