wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

Browse Source
This commit is contained in:
Blaise Tine
2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
hw/rtl/cache/VX_bank.v vendored
View File

@@ -47,7 +47,7 @@ module VX_bank #(
parameter CORE_TAG_ID_BITS = 0,
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = 1
parameter SNP_TAG_WIDTH = 1
) (
`SCOPE_IO_VX_bank
@@ -88,12 +88,12 @@ module VX_bank #(
input wire snp_req_valid,
input wire [`LINE_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_invalidate,
input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop Response
output wire snp_rsp_valid,
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// Misses
@@ -142,13 +142,13 @@ module VX_bank #(
wire [`LINE_ADDR_WIDTH-1:0] snrq_addr_st0;
wire snrq_invalidate_st0;
wire [SNP_REQ_TAG_WIDTH-1:0] snrq_tag_st0;
wire [SNP_TAG_WIDTH-1:0] snrq_tag_st0;
wire snp_req_fire = snp_req_valid && snp_req_ready;
assign snp_req_ready = !snrq_full;
VX_generic_queue #(
.DATAW(`LINE_ADDR_WIDTH + 1 + SNP_REQ_TAG_WIDTH),
.DATAW(`LINE_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE(SNRQ_SIZE)
) snp_req_queue (
.clk (clk),
@@ -352,7 +352,7 @@ module VX_bank #(
|| ((miss_st3 || force_miss_st3) && (addr_st3 == addr_st0));
`ifdef DBG_CACHE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = inst_meta_st0;
end else begin
assign {debug_pc_st0, debug_rd_st0, debug_wid_st0, debug_tagid_st0, debug_rw_st0, debug_byteen_st0, debug_tid_st0} = 0;
@@ -371,7 +371,7 @@ module VX_bank #(
);
`ifdef DBG_CACHE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1;
end else begin
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = 0;
@@ -474,7 +474,7 @@ module VX_bank #(
);
`ifdef DBG_CACHE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = inst_meta_st2;
end else begin
assign {debug_pc_st2, debug_rd_st2, debug_wid_st2, debug_tagid_st2, debug_rw_st2, debug_byteen_st2, debug_tid_st2} = 0;
@@ -574,7 +574,7 @@ module VX_bank #(
);
`ifdef DBG_CACHE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3, debug_rw_st3, debug_byteen_st3, debug_tid_st3} = inst_meta_st3;
end else begin
assign {debug_pc_st3, debug_rd_st3, debug_wid_st3, debug_tagid_st3, debug_rw_st3, debug_byteen_st3, debug_tid_st3} = 0;
@@ -621,7 +621,7 @@ module VX_bank #(
.NUM_REQUESTS (NUM_REQUESTS),
.MRVQ_SIZE (MRVQ_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
) cache_miss_resrv (
.clk (clk),
.reset (reset),
@@ -803,12 +803,12 @@ module VX_bank #(
wire snpq_pop = snp_rsp_valid && snp_rsp_ready;
wire [SNP_REQ_TAG_WIDTH-1:0] snpq_tag_st3 = SNP_REQ_TAG_WIDTH'(req_tag_st3);
wire [SNP_TAG_WIDTH-1:0] snpq_tag_st3 = SNP_TAG_WIDTH'(req_tag_st3);
if (FLUSH_ENABLE) begin
VX_generic_queue #(
.DATAW(SNP_REQ_TAG_WIDTH),
.SIZE(SNPQ_SIZE)
.DATAW (SNP_TAG_WIDTH),
.SIZE (SNPQ_SIZE)
) snp_rsp_queue (
.clk (clk),
.reset (reset),

129
hw/rtl/cache/VX_cache.v vendored
View File

@@ -39,9 +39,6 @@ module VX_cache #(
// Enable cache flush
parameter FLUSH_ENABLE = 1,
// Enable snoop forwarding
parameter SNOOP_FORWARDING = 1,
// core request tag size
parameter CORE_TAG_WIDTH = 4,
@@ -51,14 +48,8 @@ module VX_cache #(
// dram request tag size
parameter DRAM_TAG_WIDTH = 28,
// Number of snoop forwarding requests
parameter NUM_SNP_REQUESTS = (SNOOP_FORWARDING ? 4 : 1),
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = (SNOOP_FORWARDING ? 4 : 1),
// Snooping forward tag width
parameter SNP_FWD_TAG_WIDTH = (SNOOP_FORWARDING ? 4 : 1)
parameter SNP_TAG_WIDTH = 1
) (
`SCOPE_IO_VX_cache
@@ -99,28 +90,14 @@ module VX_cache #(
input wire snp_req_valid,
input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_invalidate,
input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// Snoop Forwarding out
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_valid,
output wire [NUM_SNP_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_invalidate,
output wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdout_tag,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_SNP_REQUESTS-1:0] snp_fwdout_ready,
// Snoop forwarding in
input wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_valid,
input wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
`IGNORE_WARNINGS_END
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready,
output wire [NUM_BANKS-1:0] miss_vec
);
@@ -146,72 +123,16 @@ module VX_cache #(
wire [NUM_BANKS-1:0] per_bank_snp_req_ready;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid;
wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0][SNP_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_miss;
assign miss_vec = per_bank_miss;
wire snp_req_valid_qual;
wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr_qual;
wire snp_req_invalidate_qual;
wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag_qual;
wire snp_req_ready_qual;
if (SNOOP_FORWARDING) begin
VX_snp_forwarder #(
.CACHE_ID (CACHE_ID),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_REQUESTS (NUM_SNP_REQUESTS),
.SNRQ_SIZE (SNRQ_SIZE),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
) snp_forwarder (
.clk (clk),
.reset (reset),
.snp_req_valid (snp_req_valid),
.snp_req_addr (snp_req_addr),
.snp_req_invalidate (snp_req_invalidate),
.snp_req_tag (snp_req_tag),
.snp_req_ready (snp_req_ready),
.snp_rsp_valid (snp_req_valid_qual),
.snp_rsp_addr (snp_req_addr_qual),
.snp_rsp_invalidate (snp_req_invalidate_qual),
.snp_rsp_tag (snp_req_tag_qual),
.snp_rsp_ready (snp_req_ready_qual),
.snp_fwdout_valid (snp_fwdout_valid),
.snp_fwdout_addr (snp_fwdout_addr),
.snp_fwdout_invalidate(snp_fwdout_invalidate),
.snp_fwdout_tag (snp_fwdout_tag),
.snp_fwdout_ready (snp_fwdout_ready),
.snp_fwdin_valid (snp_fwdin_valid),
.snp_fwdin_tag (snp_fwdin_tag),
.snp_fwdin_ready (snp_fwdin_ready)
);
end else begin
assign snp_fwdout_valid = 0;
assign snp_fwdout_addr = 0;
assign snp_fwdout_invalidate = 0;
assign snp_fwdout_tag = 0;
assign snp_fwdin_ready = 0;
assign snp_req_valid_qual = snp_req_valid;
assign snp_req_addr_qual = snp_req_addr;
assign snp_req_invalidate_qual = snp_req_invalidate;
assign snp_req_tag_qual = snp_req_tag;
assign snp_req_ready = snp_req_ready_qual;
end
assign miss_vec = per_bank_miss;
if (NUM_BANKS == 1) begin
assign snp_req_ready_qual = per_bank_snp_req_ready;
assign snp_req_ready = per_bank_snp_req_ready;
end else begin
assign snp_req_ready_qual = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr_qual)];
assign snp_req_ready = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr)];
end
VX_cache_core_req_bank_sel #(
@@ -221,14 +142,18 @@ module VX_cache #(
.NUM_REQUESTS (NUM_REQUESTS)
) cache_core_req_bank_sel (
.core_req_valid (core_req_valid),
.per_bank_ready (per_bank_core_req_ready),
.core_req_addr (core_req_addr),
.core_req_ready (core_req_ready),
.per_bank_valid (per_bank_valid),
.core_req_ready (core_req_ready)
.per_bank_ready (per_bank_core_req_ready)
);
assign dram_req_tag = dram_req_addr;
assign dram_rsp_ready = (& per_bank_dram_rsp_ready);
if (NUM_BANKS == 1) begin
assign dram_rsp_ready = per_bank_dram_rsp_ready;
end else begin
assign dram_rsp_ready = per_bank_dram_rsp_ready[`DRAM_ADDR_BANK(dram_rsp_tag)];
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid;
@@ -260,11 +185,11 @@ module VX_cache #(
wire curr_bank_snp_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
wire curr_bank_snp_req_invalidate;
wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_req_tag;
wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_req_tag;
wire curr_bank_snp_req_ready;
wire curr_bank_snp_rsp_valid;
wire [SNP_REQ_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
wire [SNP_TAG_WIDTH-1:0] curr_bank_snp_rsp_tag;
wire curr_bank_snp_rsp_ready;
wire curr_bank_miss;
@@ -310,14 +235,14 @@ module VX_cache #(
// Snoop request
if (NUM_BANKS == 1) begin
assign curr_bank_snp_req_valid = snp_req_valid_qual;
assign curr_bank_snp_req_addr = snp_req_addr_qual;
assign curr_bank_snp_req_valid = snp_req_valid;
assign curr_bank_snp_req_addr = snp_req_addr;
end else begin
assign curr_bank_snp_req_valid = snp_req_valid_qual && (`DRAM_ADDR_BANK(snp_req_addr_qual) == i);
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr_qual);
assign curr_bank_snp_req_valid = snp_req_valid && (`DRAM_ADDR_BANK(snp_req_addr) == i);
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr);
end
assign curr_bank_snp_req_invalidate = snp_req_invalidate_qual;
assign curr_bank_snp_req_tag = snp_req_tag_qual;
assign curr_bank_snp_req_invalidate = snp_req_invalidate;
assign curr_bank_snp_req_tag = snp_req_tag;
assign per_bank_snp_req_ready[i] = curr_bank_snp_req_ready;
// Snoop response
@@ -348,7 +273,7 @@ module VX_cache #(
.WRITE_ENABLE (WRITE_ENABLE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
) bank (
`SCOPE_BIND_VX_cache_bank(i)
@@ -459,9 +384,9 @@ module VX_cache #(
if (FLUSH_ENABLE) begin
VX_snp_rsp_arb #(
.NUM_BANKS (NUM_BANKS),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
.NUM_BANKS (NUM_BANKS),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.SNP_TAG_WIDTH (SNP_TAG_WIDTH)
) snp_rsp_arb (
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -7,7 +7,7 @@
`include "VX_define.vh"
`endif
`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH)
`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_TAG_WIDTH)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)

40
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -11,27 +11,43 @@ module VX_cache_core_req_bank_sel #(
parameter NUM_REQUESTS = 1
) (
input wire [NUM_REQUESTS-1:0] core_req_valid,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
`IGNORE_WARNINGS_END
input wire [NUM_BANKS-1:0] per_bank_ready,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
output wire core_req_ready,
output wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid,
output wire core_req_ready
input wire [NUM_BANKS-1:0] per_bank_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0] per_bank_ready_sel;
reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0] per_bank_ready_ignore;
reg [NUM_BANKS-1:0] per_bank_ready_other;
always @(*) begin
per_bank_valid_r = 0;
per_bank_ready_sel = {NUM_BANKS{1'b1}};
per_bank_valid_r = 0;
per_bank_ready_other = {NUM_BANKS{1'b1}};
per_bank_ready_ignore = {NUM_BANKS{1'b1}};
for (integer i = 0; i < NUM_BANKS; i++) begin
for (integer j = 0; j < NUM_BANKS; j++) begin
if (i != j)
per_bank_ready_other[i] &= (per_bank_ready[j] | per_bank_ready_ignore[j]);
end
end
for (integer i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valid_r[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
per_bank_ready_sel[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 0;
per_bank_ready_ignore[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 1'b0;
end
end
assign per_bank_valid = per_bank_valid_r;
assign core_req_ready = & (per_bank_ready | per_bank_ready_sel);
for (genvar i = 0; i < NUM_BANKS; i++) begin
for (genvar j = 0; j < NUM_REQUESTS; j++) begin
assign per_bank_valid[i][j] = per_bank_valid_r[i][j] & per_bank_ready_other[i];
end
end
assign core_req_ready = & (per_bank_ready | per_bank_ready_ignore);
end else begin
`UNUSED_VAR (core_req_addr)
assign per_bank_valid = core_req_valid;
assign core_req_ready = per_bank_ready;
end

2
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -17,7 +17,7 @@ module VX_cache_miss_resrv #(
// core request tag size
parameter CORE_TAG_WIDTH = 1,
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = 1,
parameter SNP_TAG_WIDTH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
) (

110
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -1,33 +1,33 @@
`include "VX_cache_config.vh"
module VX_snp_forwarder #(
parameter CACHE_ID = 0,
parameter BANK_LINE_SIZE = 1,
parameter NUM_REQUESTS = 1,
parameter SNRQ_SIZE = 1,
parameter SNP_REQ_TAG_WIDTH = 1,
parameter SNP_FWD_TAG_WIDTH = 1
parameter CACHE_ID = 0,
parameter SRC_ADDR_WIDTH = 1,
parameter DST_ADDR_WIDTH = 1,
parameter NUM_REQUESTS = 1,
parameter SNP_TAG_WIDTH = 1,
parameter SNRQ_SIZE = 1
) (
input wire clk,
input wire reset,
// Snoop request
input wire snp_req_valid,
input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire [SRC_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_invalidate,
input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
input wire [SNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// Snoop response
output wire snp_rsp_valid,
output wire [`DRAM_ADDR_WIDTH-1:0] snp_rsp_addr,
output wire [SRC_ADDR_WIDTH-1:0] snp_rsp_addr,
output wire snp_rsp_invalidate,
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// Snoop Forwarding out
output wire [NUM_REQUESTS-1:0] snp_fwdout_valid,
output wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQUESTS-1:0][DST_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQUESTS-1:0] snp_fwdout_invalidate,
output wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdout_tag,
input wire [NUM_REQUESTS-1:0] snp_fwdout_ready,
@@ -37,30 +37,37 @@ module VX_snp_forwarder #(
input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
);
localparam ADDR_DIFF = DST_ADDR_WIDTH - SRC_ADDR_WIDTH;
localparam NUM_REQUESTS_QUAL = NUM_REQUESTS * (1 << ADDR_DIFF);
localparam REQ_QUAL_BITS = `LOG2UP(NUM_REQUESTS_QUAL);
`STATIC_ASSERT(NUM_REQUESTS > 1, ("invalid value"))
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
reg [REQ_QUAL_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
wire [`LOG2UP(SNRQ_SIZE)-1:0] sfq_write_addr, sfq_read_addr;
wire sfq_acquire, sfq_release, sfq_full;
wire [`LOG2UP(SNRQ_SIZE)-1:0] fwdout_tag;
reg [NUM_REQUESTS-1:0] snp_fwdout_ready_other;
wire fwdout_ready;
wire fwdin_valid;
wire [`LOG2UP(SNRQ_SIZE)-1:0] fwdin_tag;
wire fwdin_valid;
wire fwdin_ready = snp_rsp_ready || (1 != pending_cntrs[sfq_read_addr]);
wire fwdin_fire = fwdin_valid && fwdin_ready;
wire fwdout_ready = (& snp_fwdout_ready);
assign snp_rsp_valid = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]); // send response
assign snp_rsp_valid = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]);
assign sfq_read_addr = fwdin_tag;
assign sfq_acquire = snp_req_valid && !sfq_full && fwdout_ready;
assign sfq_release = snp_rsp_valid && snp_rsp_ready;
wire snp_req_ready_unqual = !sfq_full && fwdout_ready;
VX_cam_buffer #(
.DATAW (`DRAM_ADDR_WIDTH + 1 + SNP_REQ_TAG_WIDTH),
.DATAW (SRC_ADDR_WIDTH + 1 + SNP_TAG_WIDTH),
.SIZE (SNRQ_SIZE)
) snp_fwd_cam (
.clk (clk),
@@ -75,9 +82,54 @@ module VX_snp_forwarder #(
.full (sfq_full)
);
wire [DST_ADDR_WIDTH-1:0] snp_req_addr_qual;
wire dispatch_ready;
if (ADDR_DIFF != 0) begin
reg [`LOG2UP(SNRQ_SIZE)-1:0] fwdout_tag_r;
reg [DST_ADDR_WIDTH-1:0] snp_req_addr_r;
reg dispatch_ready_r;
reg use_cter_r;
always @(posedge clk) begin
if (reset) begin
dispatch_ready_r <= 0;
use_cter_r <= 0;
end else begin
if (snp_req_valid && snp_req_ready_unqual) begin
if (snp_req_addr_r[ADDR_DIFF-1:0] == ((1 << ADDR_DIFF)-2)) begin
dispatch_ready_r <= 1;
end
if (snp_req_addr_r[ADDR_DIFF-1:0] == ((1 << ADDR_DIFF)-1)) begin
dispatch_ready_r <= 0;
use_cter_r <= 0;
end else begin
use_cter_r <= 1;
end
end
end
if (snp_req_valid && snp_req_ready_unqual) begin
snp_req_addr_r <= snp_req_addr_qual + DST_ADDR_WIDTH'(1'b1);
end
if (!use_cter_r) begin
fwdout_tag_r <= sfq_write_addr;
end
end
assign sfq_acquire = snp_req_valid && snp_req_ready_unqual && !use_cter_r;
assign fwdout_tag = use_cter_r ? fwdout_tag_r : sfq_write_addr;
assign snp_req_addr_qual = use_cter_r ? snp_req_addr_r : {snp_req_addr, ADDR_DIFF'(0)};
assign dispatch_ready = dispatch_ready_r;
end else begin
assign sfq_acquire = snp_req_valid && snp_req_ready;
assign fwdout_tag = sfq_write_addr;
assign snp_req_addr_qual = snp_req_addr;
assign dispatch_ready = 1'b1;
end
always @(posedge clk) begin
if (sfq_acquire) begin
pending_cntrs[sfq_write_addr] <= NUM_REQUESTS;
pending_cntrs[sfq_write_addr] <= NUM_REQUESTS_QUAL;
end
if (fwdin_fire) begin
pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1;
@@ -85,13 +137,25 @@ module VX_snp_forwarder #(
end
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign snp_fwdout_valid[i] = snp_req_valid && snp_req_ready;
assign snp_fwdout_addr[i] = snp_req_addr;
assign snp_fwdout_valid[i] = snp_req_valid && snp_fwdout_ready_other[i] && !sfq_full;
assign snp_fwdout_addr[i] = snp_req_addr_qual;
assign snp_fwdout_invalidate[i] = snp_req_invalidate;
assign snp_fwdout_tag[i] = sfq_write_addr;
assign snp_fwdout_tag[i] = fwdout_tag;
end
assign snp_req_ready = !sfq_full && fwdout_ready;
always @(*) begin
snp_fwdout_ready_other = {NUM_REQUESTS{1'b1}};
for (integer i = 0; i < NUM_REQUESTS; i++) begin
for (integer j = 0; j < NUM_REQUESTS; j++) begin
if (i != j)
snp_fwdout_ready_other[i] &= snp_fwdout_ready[j];
end
end
end
assign fwdout_ready = (& snp_fwdout_ready);
assign snp_req_ready = snp_req_ready_unqual && dispatch_ready;
if (NUM_REQUESTS > 1) begin
wire sel_valid;

8
hw/rtl/cache/VX_snp_rsp_arb.v vendored
View File

@@ -3,17 +3,17 @@
module VX_snp_rsp_arb #(
parameter NUM_BANKS = 1,
parameter BANK_LINE_SIZE = 1,
parameter SNP_REQ_TAG_WIDTH = 1
parameter SNP_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid,
input wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag,
input wire [NUM_BANKS-1:0][SNP_TAG_WIDTH-1:0] per_bank_snp_rsp_tag,
output wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready,
output wire snp_rsp_valid,
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
output wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready
);
if (NUM_BANKS > 1) begin
@@ -35,7 +35,7 @@ module VX_snp_rsp_arb #(
wire stall = ~snp_rsp_ready && snp_rsp_valid;
VX_generic_register #(
.N(1 + SNP_REQ_TAG_WIDTH),
.N(1 + SNP_TAG_WIDTH),
.PASSTHRU(NUM_BANKS <= 2)
) pipe_reg (
.clk (clk),