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fix l2 cache issues

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This commit is contained in:
Blaise Tine
2020-06-04 18:34:14 -04:00
parent ea890b457d
commit 171d46b501
11 changed files with 300 additions and 260 deletions
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30
hw/rtl/cache/VX_bank.v vendored
View File

@@ -459,7 +459,7 @@ module VX_bank #(
end
)
wire qual_valid_st1e_2 = valid_st1e && !is_fill_st1[STAGE_1_CYCLES-1];
wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e;
wire from_mrvq_st1e_st2 = from_mrvq_st1e;
wire valid_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;
@@ -721,49 +721,49 @@ module VX_bank #(
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (core_req_valid && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_wb_req_addr), dram_wb_req_data);
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_wb_req_addr), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
$display("%t: bank%0d-%0d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
end
end else begin
always_ff @(posedge clk) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
$display("%t: bank%0d-%0d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
$display("%t: bank%0d-%0d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
$display("%t: bank%0d-%0d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%01d%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
$display("%t: bank%0d-%0d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
$display("%t: bank%0d-%0d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
$display("%t: bank%0d-%0d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
$display("%t: bank%0d-%0d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end
end
end

22
hw/rtl/cache/VX_cache.v vendored
View File

@@ -208,13 +208,13 @@ module VX_cache #(
assign snp_req_addr_qual = snp_req_addr;
assign snp_req_tag_qual = snp_req_tag;
assign snp_req_ready = snp_req_ready_qual;
end
end
assign dram_req_tag = dram_req_addr;
assign core_req_ready = (& per_bank_core_req_ready);
assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready);
assign snp_req_ready_qual = (& per_bank_snp_req_ready);
if (NUM_BANKS == 1) begin
assign snp_req_ready_qual = per_bank_snp_req_ready;
end else begin
assign snp_req_ready_qual = per_bank_snp_req_ready[`DRAM_ADDR_BANK(snp_req_addr_qual)];
end
VX_cache_core_req_bank_sel #(
.BANK_LINE_SIZE (BANK_LINE_SIZE),
@@ -223,11 +223,17 @@ module VX_cache #(
.NUM_REQUESTS (NUM_REQUESTS)
) cache_core_req_bank_sel (
.core_req_valid (core_req_valid),
.per_bank_ready (per_bank_core_req_ready),
.core_req_addr (core_req_addr),
.per_bank_valid (per_bank_valid)
.per_bank_valid (per_bank_valid),
.core_req_ready (core_req_ready)
);
assign dram_req_tag = dram_req_addr;
assign dram_rsp_ready = (| per_bank_dram_fill_rsp_ready);
genvar i;
generate
for (i = 0; i < NUM_BANKS; i++) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valid;
@@ -270,7 +276,7 @@ module VX_cache #(
wire curr_bank_core_req_ready;
// Core Req
assign curr_bank_core_req_valid = per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}};
assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}});
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_rw = core_req_rw;
assign curr_bank_core_req_byteen = core_req_byteen;

21
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -11,28 +11,35 @@ module VX_cache_core_req_bank_sel #(
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 0
) (
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_valid,
`IGNORE_WARNINGS_BEGIN
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
`IGNORE_WARNINGS_END
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid
input wire [NUM_BANKS-1:0] per_bank_ready,
output reg [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid,
output wire core_req_ready
);
integer i;
if (NUM_BANKS == 1) begin
always @(*) begin
always @(*) begin
per_bank_valid = 0;
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valid[0][i] = core_req_valid[i];
end
end
end else begin
end
assign core_req_ready = per_bank_ready;
end else begin
reg [NUM_BANKS-1:0] per_bank_ready_sel;
always @(*) begin
per_bank_valid = 0;
per_bank_ready_sel = {NUM_BANKS{1'b1}};
for (i = 0; i < NUM_REQUESTS; i++) begin
per_bank_valid[core_req_addr[i][`BANK_SELECT_ADDR_RNG]][i] = core_req_valid[i];
per_bank_ready_sel[core_req_addr[i][`BANK_SELECT_ADDR_RNG]] = 0;
end
end
end
assign core_req_ready = & (per_bank_ready | per_bank_ready_sel);
end
endmodule

25
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -72,10 +72,6 @@ module VX_cache_miss_resrv #(
wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
`IGNORE_WARNINGS_BEGIN
wire [31:0] make_ready_push_full;
`IGNORE_WARNINGS_END
reg [MRVQ_SIZE-1:0] make_ready;
reg [MRVQ_SIZE-1:0] make_ready_push;
reg [MRVQ_SIZE-1:0] valid_address_match;
@@ -93,24 +89,21 @@ module VX_cache_miss_resrv #(
wire dequeue_possible = valid_table[schedule_ptr] && ready_table[schedule_ptr];
wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = schedule_ptr;
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_valid_st0 = dequeue_possible;
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_rw_st0, miss_resrv_byteen_st0, miss_resrv_wsel_st0, miss_resrv_is_snp_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq && (MRVQ_SIZE != 2);
wire mrvq_push = miss_add && enqueue_possible && !from_mrvq;
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire recover_state = miss_add && from_mrvq;
wire increment_head = !miss_add && from_mrvq;
wire update_ready = (|make_ready);
wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
assign make_ready_push_full = ({31'b0, qual_mrvq_init} << enqueue_index);
assign make_ready_push = make_ready_push_full[MRVQ_SIZE-1:0];
assign make_ready_push = (MRVQ_SIZE'(qual_mrvq_init)) << enqueue_index;
always @(posedge clk) begin
if (reset) begin
@@ -160,12 +153,12 @@ module VX_cache_miss_resrv #(
integer j;
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop) begin
$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, {addr_table[j], `BASE_ADDR_BITS'(0)});
end
@@ -175,12 +168,12 @@ module VX_cache_miss_resrv #(
end
end else begin
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop) begin
$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
if (mrvq_push || mrvq_pop || increment_head || recover_state) begin
$write("%t: bank%0d-%0d msrq: push=%b pop=%b incr=%d recv=%d", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop, increment_head, recover_state);
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end

18
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -34,6 +34,8 @@ module VX_snp_forwarder #(
input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
);
`STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value");
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
reg [`REQS_BITS-1:0] fwdin_sel;
@@ -43,12 +45,12 @@ module VX_snp_forwarder #(
wire fwdin_valid;
wire [`LOG2UP(SNRQ_SIZE)-1:0] fwdin_tag;
wire fwdin_ready = snp_rsp_ready;
wire fwdin_taken = fwdin_valid && fwdin_ready;
wire fwdin_ready = snp_rsp_ready || (1 != pending_cntrs[sfq_read_addr]);
wire fwdin_fire = fwdin_valid && fwdin_ready;
wire fwdout_ready = (& snp_fwdout_ready);
assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[sfq_read_addr]); // send response
assign snp_rsp_valid = fwdin_valid && (1 == pending_cntrs[sfq_read_addr]); // send response
assign sfq_read_addr = fwdin_tag;
@@ -77,7 +79,7 @@ module VX_snp_forwarder #(
if (sfq_push) begin
pending_cntrs[sfq_write_addr] <= NUM_REQUESTS;
end
if (fwdin_taken) begin
if (fwdin_fire) begin
pending_cntrs[sfq_read_addr] <= pending_cntrs[sfq_read_addr] - 1;
assert(sfq_read_addr == dbg_sfq_write_addr);
end
@@ -112,16 +114,16 @@ module VX_snp_forwarder #(
`ifdef DBG_PRINT_CACHE_SNP
always_ff @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: cache%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_req_addr), snp_req_tag);
$display("%t: cache%0d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_req_addr), snp_req_tag);
end
if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("%t: cache%01d snp fwd_out: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_fwdout_addr[0]), snp_fwdout_tag[0]);
$display("%t: cache%0d snp fwd_out: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_fwdout_addr[0]), snp_fwdout_tag[0]);
end
if (fwdin_valid && fwdin_ready) begin
$display("%t: cache%01d snp fwd_in[%01d]: tag=%0h", $time, CACHE_ID, fwdin_sel, fwdin_tag);
$display("%t: cache%0d snp fwd_in[%01d]: tag=%0h", $time, CACHE_ID, fwdin_sel, fwdin_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: cache%01d snp rsp: addr=%0h, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_tag);
$display("%t: cache%0d snp rsp: addr=%0h, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_tag);
end
end
`endif