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scope fixes

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This commit is contained in:
Blaise Tine
2020-06-08 04:25:28 -07:00
parent abc09eb1a3
commit 170c88f295
14 changed files with 532 additions and 95 deletions
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28
hw/rtl/VX_define.vh
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@@ -283,7 +283,7 @@
///////////////////////////////////////////////////////////////////////////////
`ifdef SCOPE
`define SCOPE_SIGNALS_LIST() \
`define SCOPE_SIGNALS_LIST \
scope_icache_req_valid, \
scope_icache_req_tag, \
scope_icache_req_ready, \
@@ -304,7 +304,7 @@
scope_dram_rsp_ready, \
scope_schedule_delay
`define SCOPE_SIGNALS_DECL() \
`define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \
wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
@@ -325,7 +325,7 @@
wire scope_dram_rsp_ready; \
wire scope_schedule_delay;
`define SCOPE_SIGNALS_IO() \
`define SCOPE_SIGNALS_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_icache_req_valid, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
@@ -345,10 +345,10 @@
output wire scope_dram_rsp_valid, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag, \
output wire scope_dram_rsp_ready, \
output wire scope_schedule_delay \
output wire scope_schedule_delay, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_ATTACH() \
`define SCOPE_SIGNALS_ATTACH \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
@@ -361,18 +361,18 @@
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready), \
.scope_dram_req_valid (scope_dram_req_valid), \
.scope_dram_req_tag (scope_dram_req_tag), \
.scope_dram_req_ready (scope_dram_req_ready), \
.scope_dram_rsp_valid (scope_dram_rsp_valid), \
.scope_dram_rsp_tag (scope_dram_rsp_tag), \
.scope_dram_rsp_ready (scope_dram_rsp_ready), \
.scope_schedule_delay (scope_schedule_delay)
.scope_dram_req_valid (scope_dram_req_valid), \
.scope_dram_req_tag (scope_dram_req_tag), \
.scope_dram_req_ready (scope_dram_req_ready), \
.scope_dram_rsp_valid (scope_dram_rsp_valid), \
.scope_dram_rsp_tag (scope_dram_rsp_tag), \
.scope_dram_rsp_ready (scope_dram_rsp_ready), \
.scope_schedule_delay (scope_schedule_delay),
`define SCOPE_ASSIGN(d,s) assign d = s
`else
`define SCOPE_SIGNALS_IO()
`define SCOPE_SIGNALS_ATTACH()
`define SCOPE_SIGNALS_IO
`define SCOPE_SIGNALS_ATTACH
`define SCOPE_ASSIGN(d,s)
`endif

2
hw/rtl/VX_pipeline.v
View File

@@ -3,7 +3,7 @@
module VX_pipeline #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_IO(),
`SCOPE_SIGNALS_IO
// Clock
input wire clk,

4
hw/rtl/Vortex.v
View File

@@ -3,7 +3,7 @@
module Vortex #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_IO(),
`SCOPE_SIGNALS_IO
// Clock
input wire clk,
@@ -165,7 +165,7 @@ module Vortex #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_SIGNALS_ATTACH(),
`SCOPE_SIGNALS_ATTACH
.clk(clk),
.reset(reset),

4
hw/rtl/Vortex_Cluster.v
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@@ -3,7 +3,7 @@
module Vortex_Cluster #(
parameter CLUSTER_ID = 0
) (
`SCOPE_SIGNALS_IO(),
`SCOPE_SIGNALS_IO
// Clock
input wire clk,
@@ -108,7 +108,7 @@ module Vortex_Cluster #(
Vortex #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) vortex_core (
`SCOPE_SIGNALS_ATTACH(),
`SCOPE_SIGNALS_ATTACH
.clk (clk),
.reset (reset),

6
hw/rtl/Vortex_Socket.v
View File

@@ -1,7 +1,7 @@
`include "VX_define.vh"
module Vortex_Socket (
`SCOPE_SIGNALS_IO(),
`SCOPE_SIGNALS_IO
// Clock
input wire clk,
@@ -64,7 +64,7 @@ module Vortex_Socket (
Vortex_Cluster #(
.CLUSTER_ID(`L3CACHE_ID)
) Vortex_Cluster (
`SCOPE_SIGNALS_ATTACH(),
`SCOPE_SIGNALS_ATTACH
.clk (clk),
.reset (reset),
@@ -151,7 +151,7 @@ module Vortex_Socket (
Vortex_Cluster #(
.CLUSTER_ID(i)
) Vortex_Cluster (
`SCOPE_SIGNALS_ATTACH(),
`SCOPE_SIGNALS_ATTACH
.clk (clk),
.reset (reset),

139
hw/rtl/libs/VX_scope.v
View File

@@ -1,87 +1,146 @@
`include "VX_define.vh"
module VX_scope #(
parameter DATAW = 64,
parameter BUSW = 64,
parameter SIZE = 1024
parameter SIZE = 256
) (
input wire clk,
input wire reset,
input wire start,
input wire [DATAW-1:0] data_in,
input wire [BUSW-1:0] bus_in,
output wire [BUSW-1:0] bus_out,
input wire [BUSW-1:0] bus_in,
output reg [BUSW-1:0] bus_out,
input wire bus_write,
input wire bus_read
);
typedef enum logic[2:0] {
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_DEPTH,
CMD_SET_DELAY,
CMD_SET_DURATION,
CMD_SET_RESERVED1,
CMD_SET_RESERVED2
} cmd_t;
typedef enum logic[1:0] {
GET_VALID,
GET_DATA,
GET_WIDTH,
GET_DEPTH
} cmd_get_t;
reg [DATAW-1:0] mem [SIZE-1:0];
//reg [63:0] offsets [SIZE-1:0];
reg [`CLOG2(SIZE)-1:0] raddr, waddr;
reg started, running, done;
reg [BUSW-1:0] delay_cntr;
reg data_valid, data_end;
reg [`CLOG2(SIZE)-1:0] raddr, waddr, waddr_end;
reg [`LOG2UP(DATAW)-1:0] read_offset;
wire [BUSW-3:0] data_part;
reg start_wait, recording, data_valid;
reg [BUSW-3:0] delay_val, delay_cntr;
reg [1:0] out_cmd;
wire [2:0] cmd_type;
wire [BUSW-4:0] cmd_data;
assign {cmd_data, cmd_type} = bus_in;
always @(posedge clk) begin
if (reset) begin
raddr <= 0;
waddr <= 0;
started <= 0;
running <= 0;
done <= 0;
start_wait <= 0;
recording <= 0;
delay_cntr <= 0;
read_offset <= 0;
data_valid <= 0;
out_cmd <= $bits(out_cmd)'(CMD_GET_VALID);
delay_val <= 0;
waddr_end <= $bits(waddr)'(SIZE-1);
end else begin
if (bus_write) begin
delay_cntr <= bus_in;
case (cmd_type)
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_DEPTH: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_DURATION: waddr_end <= $bits(waddr)'(cmd_data);
default:;
endcase
end
if (start) begin
started <= 1;
end
if (start || started) begin
if (0 == delay_cntr) begin
running <= 1;
if (start) begin
waddr <= 0;
if (0 == delay_val) begin
start_wait <= 0;
recording <= 1;
delay_cntr <= 0;
end else begin
delay_cntr <= delay_cntr - 1;
start_wait <= 1;
recording <= 0;
delay_cntr <= delay_val;
end
end
if (running && !done) begin
if (start_wait) begin
delay_cntr <= delay_cntr - 1;
if (1 == delay_cntr) begin
start_wait <= 0;
recording <= 1;
end
end
if (recording) begin
mem[waddr] <= data_in;
waddr <= waddr + 1;
if (waddr == $bits(waddr)'(SIZE-1)) begin
done <= 1;
if (waddr == waddr_end) begin
recording <= 0;
data_valid <= 1;
end
end
if (bus_read) begin
if (DATAW > (BUSW-2)) begin
if (read_offset < $bits(read_offset)'(DATAW-(BUSW-2))) begin
read_offset <= read_offset + $bits(read_offset)'(BUSW-2);
if (bus_read
&& (out_cmd == GET_DATA)
&& data_valid) begin
if (DATAW > BUSW) begin
if (read_offset < $bits(read_offset)'(DATAW-BUSW)) begin
read_offset <= read_offset + $bits(read_offset)'(BUSW);
end else begin
read_offset <= 0;
raddr <= raddr + 1;
end
read_offset <= 0;
if (raddr == waddr_end) begin
data_valid <= 0;
end
end
end else begin
raddr <= raddr + 1;
end
raddr <= raddr + 1;
if (raddr == waddr_end) begin
data_valid <= 0;
end
end
end
end
end
assign data_valid = (waddr != 0) && (raddr <= waddr);
always @(*) begin
case (out_cmd)
GET_VALID : bus_out = BUSW'(data_valid);
GET_WIDTH : bus_out = BUSW'(DATAW);
GET_DEPTH : bus_out = BUSW'(waddr_end) + BUSW'(1);
default : bus_out = (BUSW)'(mem[raddr] >> read_offset);
endcase
end
assign data_end = (0 == read_offset) || (raddr == waddr);
assign data_part = (BUSW-2)'(mem[raddr] >> read_offset);
assign bus_out = {data_valid, data_end, data_part};
always_ff @(posedge clk) begin
if (bus_read) begin
$display("%t: read: cmd=%0d, out=0x%0h, addr=%0d, off=%0d", $time, out_cmd, bus_out, raddr, read_offset);
end
end
endmodule