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opae rtl fixes

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This commit is contained in:
Blaise Tine
2020-05-31 14:51:42 -07:00
parent 6a3b237054
commit 16d5a8a09c
24 changed files with 547 additions and 403 deletions
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1
hw/rtl/cache/VX_cache.v vendored
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@@ -169,6 +169,7 @@ module VX_cache #(
if (SNOOP_FORWARDING) begin
VX_snp_forwarder #(
.CACHE_ID (CACHE_ID),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_REQUESTS (NUM_SNP_REQUESTS),
.SNRQ_SIZE (SNRQ_SIZE),

2
hw/rtl/cache/VX_cache_config.vh vendored
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@@ -72,8 +72,6 @@
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define BYTE_TO_WORD_ADDR(x, w) (32-`CLOG2(w))'(x >> `CLOG2(w))
`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, `BANK_SELECT_BITS'(i), `BASE_ADDR_BITS'(0)}

9
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -1,6 +1,7 @@
`include "VX_cache_config.vh"
module VX_snp_forwarder #(
parameter CACHE_ID = 0,
parameter BANK_LINE_SIZE = 0,
parameter NUM_REQUESTS = 0,
parameter SNRQ_SIZE = 0,
@@ -111,16 +112,16 @@ module VX_snp_forwarder #(
`ifdef DBG_PRINT_CACHE_SNP
always_ff @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: snp req: addr=%0h, tag=%0h", $time, {snp_req_addr, `LOG2UP(BANK_LINE_SIZE)'(0)}, snp_req_tag);
$display("%t: cache%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_req_addr), snp_req_tag);
end
if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, {snp_fwdout_addr[0], `LOG2UP(BANK_LINE_SIZE)'(0)}, snp_fwdout_tag[0]);
$display("%t: cache%01d snp fwd_out: addr=%0h, tag=%0h", $time, CACHE_ID, `DRAM_TO_BYTE_ADDR(snp_fwdout_addr[0]), snp_fwdout_tag[0]);
end
if (fwdin_valid && fwdin_ready) begin
$display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);
$display("%t: cache%01d snp fwd_in[%01d]: tag=%0h", $time, CACHE_ID, fwdin_sel, fwdin_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
$display("%t: cache%01d snp rsp: addr=%0h, tag=%0h", $time, CACHE_ID, snp_rsp_addr, snp_rsp_tag);
end
end
`endif

14
hw/rtl/cache/VX_tag_data_structure.v vendored
View File

@@ -30,12 +30,12 @@ module VX_tag_data_structure #(
input wire fill_sent
);
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_COUNT-1:0] valid;
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
assign read_dirtyb = dirtyb [read_addr];
@@ -48,9 +48,7 @@ module VX_tag_data_structure #(
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0;
dirty[i] <= 0;
dirtyb[i] <= 0;
valid[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (do_write) begin