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Fixed SM + added def SYN

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This commit is contained in:
felsabbagh3
2019-10-22 15:56:30 -04:00
parent 3cb5820ecd
commit 1645a04b1d
13 changed files with 2388 additions and 2364 deletions
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127
rtl/shared_memory/VX_shared_memory_block.v
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@@ -9,73 +9,78 @@ module VX_shared_memory_block (
);
logic [3:0][31:0] shared_memory[127:0];
//wire need_to_write = (|we);
`ifndef SYN
always @(posedge clk) begin
if(shm_write) begin
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
logic [3:0][31:0] shared_memory[127:0];
//wire need_to_write = (|we);
always @(posedge clk) begin
if(shm_write) begin
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
end
end
end
assign data_out = shm_write ? 0 : shared_memory[addr];
assign data_out = shm_write ? 0 : shared_memory[addr];
`else
wire cena = 1;
wire cenb = shm_write;
wire[3:0][31:0] write_bit_mask;
assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_128x128_wm1 first_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask),
.AB(addr),
.DB(wdata),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// wire cena = 1;
// wire cenb = shm_write;
// wire[3:0][31:0] write_bit_mask;
// assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
// assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
// assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
// assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
// // Using ASIC MEM
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_128x128_wm1 first_ram (
// .CENYA(),
// .AYA(),
// .CENYB(),
// .WENYB(),
// .AYB(),
// .QA(data_out),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena),
// .AA(addr),
// .CLKB(clk),
// .CENB(cenb),
// .WENB(write_bit_mask),
// .AB(addr),
// .DB(wdata),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule