Fixed SM + added def SYN
This commit is contained in:
felsabbagh3
@@ -16,73 +16,84 @@ module VX_priority_encoder_sm
|
||||
// To SM Module
|
||||
output reg[NB:0] out_valid,
|
||||
output reg[NB:0][31:0] out_address,
|
||||
output reg[NB:0][31:0] out_data,
|
||||
output reg[NB:0][31:0] out_data,
|
||||
|
||||
// To Processor
|
||||
output wire[NB:0][1:0] req_num,
|
||||
output reg stall,
|
||||
output wire send_data // Finished all of the requests
|
||||
output wire send_data // Finished all of the requests
|
||||
);
|
||||
|
||||
wire[NB:0][`NT_M1:0] bank_valids;
|
||||
wire[NB:0][`NT_M1:0] temp_bank_valids;
|
||||
reg[NB:0][`NT_M1:0] temp_valid; // State - If there's any ones here, then stall
|
||||
wire[NB:0] temp_stall;
|
||||
integer counter[NB:0] ;
|
||||
wire[NB:0][`NT_M1:0] mask;
|
||||
wire[NB:0] update_temp_valid;
|
||||
reg[NB:0] req_done;
|
||||
reg[`NT_M1:0] left_requests;
|
||||
|
||||
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
|
||||
.in_valids(in_valid),
|
||||
.in_addr(in_address),
|
||||
.bank_valids(bank_valids)
|
||||
);
|
||||
|
||||
genvar j;
|
||||
for(j=0; j <= NB; j++) begin
|
||||
assign temp_stall[j] = ($countones(temp_valid[j]) != 0);
|
||||
assign temp_bank_valids[j] = (temp_stall[j] || req_done[j]) ? temp_valid[j] : bank_valids[j];
|
||||
assign update_temp_valid[j] = !req_done[j] && ($countones(bank_valids[j]) > 1);
|
||||
|
||||
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
|
||||
.valids(temp_bank_valids[j]),
|
||||
.index(req_num[j]),
|
||||
.found(out_valid[j])
|
||||
);
|
||||
|
||||
VX_set_bit vx_set_bit(
|
||||
.index(req_num[j]),
|
||||
.mask (mask[j])
|
||||
);
|
||||
|
||||
assign out_address[j] = out_valid[j] ? in_address[req_num[j]] : 0;
|
||||
assign out_data[j] = out_valid[j] ? in_data[req_num[j]] : 0;
|
||||
end
|
||||
wire[`NT_M1:0] use_valid;
|
||||
|
||||
|
||||
assign stall = |temp_stall;
|
||||
assign send_data = &req_done;
|
||||
wire requests_left = (|left_requests);
|
||||
|
||||
genvar i;
|
||||
always @(posedge clk) begin
|
||||
for(i = 0; i <= NB; i = i+1) begin
|
||||
if (update_temp_valid[i]) begin
|
||||
counter[i] <= counter[i] + 1;
|
||||
if(counter[i] == 0) temp_valid[i] <= bank_valids[i] & mask[i];
|
||||
else if (counter[i] > 0) temp_valid[i] <= temp_bank_valids[i] & mask[i];
|
||||
end
|
||||
if(($countones(in_valid) > 0) && ($countones(bank_valids[i]) == 0)) begin
|
||||
req_done[i] <= 1;
|
||||
end
|
||||
else if((counter[i][2:0] == ($countones(bank_valids[i])-1))) begin
|
||||
req_done[i] <= 1;
|
||||
counter[i] <= 0;
|
||||
end
|
||||
else begin
|
||||
req_done[i] <= 0;
|
||||
assign use_valid = (requests_left) ? left_requests : in_valid;
|
||||
|
||||
|
||||
wire[NB:0][`NT_M1:0] bank_valids;
|
||||
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
|
||||
.in_valids(use_valid),
|
||||
.in_addr(in_address),
|
||||
.bank_valids(bank_valids)
|
||||
);
|
||||
|
||||
wire[NB:0] more_than_one_valid;
|
||||
|
||||
genvar curr_bank;
|
||||
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
|
||||
begin
|
||||
assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1;
|
||||
end
|
||||
|
||||
|
||||
assign stall = (|more_than_one_valid);
|
||||
assign send_data = (!stall) && (|in_valid); // change
|
||||
|
||||
wire[NB:0][1:0] internal_req_num;
|
||||
wire[NB:0] internal_out_valid;
|
||||
|
||||
|
||||
// There's one or less valid per bank
|
||||
genvar curr_bank_o;
|
||||
for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
|
||||
begin
|
||||
|
||||
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
|
||||
.valids(bank_valids[curr_bank_o]),
|
||||
.index(internal_req_num[curr_bank_o]),
|
||||
.found(internal_out_valid[curr_bank_o])
|
||||
);
|
||||
assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
|
||||
assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
|
||||
end
|
||||
|
||||
reg[`NT_M1:0] serviced;
|
||||
genvar curr_b;
|
||||
always @(*) begin
|
||||
serviced = 0;
|
||||
for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin
|
||||
serviced[internal_req_num[curr_b]] = 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign req_num = internal_req_num;
|
||||
assign out_valid = internal_out_valid;
|
||||
|
||||
|
||||
wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
|
||||
|
||||
wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
|
||||
|
||||
// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (!stall) left_requests <= 0;
|
||||
else left_requests <= new_left_requests;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -9,73 +9,78 @@ module VX_shared_memory_block (
|
||||
|
||||
);
|
||||
|
||||
logic [3:0][31:0] shared_memory[127:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
`ifndef SYN
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(shm_write) begin
|
||||
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
|
||||
logic [3:0][31:0] shared_memory[127:0];
|
||||
|
||||
//wire need_to_write = (|we);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(shm_write) begin
|
||||
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
|
||||
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
|
||||
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
|
||||
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign data_out = shm_write ? 0 : shared_memory[addr];
|
||||
assign data_out = shm_write ? 0 : shared_memory[addr];
|
||||
|
||||
`else
|
||||
|
||||
wire cena = 1;
|
||||
wire cenb = shm_write;
|
||||
|
||||
wire[3:0][31:0] write_bit_mask;
|
||||
|
||||
assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
|
||||
assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
|
||||
|
||||
// Using ASIC MEM
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
rf2_128x128_wm1 first_ram (
|
||||
.CENYA(),
|
||||
.AYA(),
|
||||
.CENYB(),
|
||||
.WENYB(),
|
||||
.AYB(),
|
||||
.QA(data_out),
|
||||
.SOA(),
|
||||
.SOB(),
|
||||
.CLKA(clk),
|
||||
.CENA(cena),
|
||||
.AA(addr),
|
||||
.CLKB(clk),
|
||||
.CENB(cenb),
|
||||
.WENB(write_bit_mask),
|
||||
.AB(addr),
|
||||
.DB(wdata),
|
||||
.EMAA(3'b011),
|
||||
.EMASA(1'b0),
|
||||
.EMAB(3'b011),
|
||||
.TENA(1'b1),
|
||||
.TCENA(1'b0),
|
||||
.TAA(5'b0),
|
||||
.TENB(1'b1),
|
||||
.TCENB(1'b0),
|
||||
.TWENB(128'b0),
|
||||
.TAB(5'b0),
|
||||
.TDB(128'b0),
|
||||
.RET1N(1'b1),
|
||||
.SIA(2'b0),
|
||||
.SEA(1'b0),
|
||||
.DFTRAMBYP(1'b0),
|
||||
.SIB(2'b0),
|
||||
.SEB(1'b0),
|
||||
.COLLDISN(1'b1)
|
||||
);
|
||||
/* verilator lint_on PINCONNECTEMPTY */
|
||||
|
||||
|
||||
|
||||
|
||||
// wire cena = 1;
|
||||
// wire cenb = shm_write;
|
||||
|
||||
// wire[3:0][31:0] write_bit_mask;
|
||||
|
||||
// assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
|
||||
// assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
|
||||
|
||||
// // Using ASIC MEM
|
||||
// /* verilator lint_off PINCONNECTEMPTY */
|
||||
// rf2_128x128_wm1 first_ram (
|
||||
// .CENYA(),
|
||||
// .AYA(),
|
||||
// .CENYB(),
|
||||
// .WENYB(),
|
||||
// .AYB(),
|
||||
// .QA(data_out),
|
||||
// .SOA(),
|
||||
// .SOB(),
|
||||
// .CLKA(clk),
|
||||
// .CENA(cena),
|
||||
// .AA(addr),
|
||||
// .CLKB(clk),
|
||||
// .CENB(cenb),
|
||||
// .WENB(write_bit_mask),
|
||||
// .AB(addr),
|
||||
// .DB(wdata),
|
||||
// .EMAA(3'b011),
|
||||
// .EMASA(1'b0),
|
||||
// .EMAB(3'b011),
|
||||
// .TENA(1'b1),
|
||||
// .TCENA(1'b0),
|
||||
// .TAA(5'b0),
|
||||
// .TENB(1'b1),
|
||||
// .TCENB(1'b0),
|
||||
// .TWENB(128'b0),
|
||||
// .TAB(5'b0),
|
||||
// .TDB(128'b0),
|
||||
// .RET1N(1'b1),
|
||||
// .SIA(2'b0),
|
||||
// .SEA(1'b0),
|
||||
// .DFTRAMBYP(1'b0),
|
||||
// .SIB(2'b0),
|
||||
// .SEB(1'b0),
|
||||
// .COLLDISN(1'b1)
|
||||
// );
|
||||
// /* verilator lint_on PINCONNECTEMPTY */
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user