PERF pipeline stalls and cache

hw/rtl/interfaces/VX_perf_cache_if.v

@@ -0,0 +1,22 @@
+`ifndef VX_PERF_CACHE_IF
+`define VX_PERF_CACHE_IF
+
+`include "VX_define.vh"
+
+interface VX_perf_cache_if ();
+
+wire [63:0]     read_miss;
+wire [63:0]     write_miss;
+wire [63:0]     dram_stall;
+wire [63:0]     dram_rsp;
+wire [63:0]     core_rsp_stall;
+wire [63:0]     msrq_stall;
+wire [63:0]     total_stall;
+wire [63:0]     total_read;
+wire [63:0]     total_write;
+wire [63:0]     total_eviction;
+wire [63:0]     dram_latency;
+
+endinterface
+
+`endif

hw/rtl/interfaces/VX_perf_pipeline_stall_if.v

@@ -0,0 +1,25 @@
+`ifndef VX_PERF_PIPELINE_STALL_IF
+`define VX_PERF_PIPELINE_STALL_IF
+
+`include "VX_define.vh"
+
+interface VX_perf_pipeline_stall_if ();
+    // from pipeline
+    wire [63:0]     icache_stall;
+    wire [63:0]     ibuffer_stall;
+    // from issue
+    wire [63:0]     scoreboard_stall;
+    // from execute
+    wire [63:0]     lsu_stall;
+    wire [63:0]     csr_stall;
+    wire [63:0]     alu_stall;
+    wire [63:0]     gpu_stall;
+    `ifdef EXT_M_ENABLE
+        wire [63:0]     mul_stall;
+    `endif
+    `ifdef EXT_F_ENABLE
+        wire [63:0]     fpu_stall;
+    `endif
+endinterface
+
+`endif