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PERF pipeline stalls and cache

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This commit is contained in:
Xandy Liu
2020-12-08 01:14:41 -05:00
parent 0d0706411d
commit 1595ff08e2
17 changed files with 843 additions and 5 deletions
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11
hw/rtl/VX_csr_unit.v
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@@ -6,6 +6,12 @@ module VX_csr_unit #(
input wire clk,
input wire reset,
// PERF: total reads
`ifdef PERF_ENABLE
VX_perf_cache_if perf_cache_if,
VX_perf_pipeline_stall_if perf_pipeline_stall_if,
`endif
VX_cmt_to_csr_if cmt_to_csr_if,
VX_fpu_to_csr_if fpu_to_csr_if,
@@ -51,6 +57,11 @@ module VX_csr_unit #(
) csr_data (
.clk (clk),
.reset (reset),
// PERF: total reads
`ifdef PERF_ENABLE
.perf_cache_if (perf_cache_if),
.perf_pipeline_stall_if (perf_pipeline_stall_if),
`endif
.cmt_to_csr_if (cmt_to_csr_if),
.fpu_to_csr_if (fpu_to_csr_if),
.read_enable (csr_pipe_req_if.valid),