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moved apae sources into rtl/afu

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This commit is contained in:
Blaise Tine
2020-12-08 04:59:11 -08:00
parent d5fa82f5e4
commit 14baec86d5
18 changed files with 35 additions and 1710 deletions
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16
hw/opae/Makefile
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@@ -1,6 +1,6 @@
ASE_BUILD_DIR=build_ase
FPGA_BUILD_DIR=build_fpga
RTL_DIR=../rtl
all: ase-1c
@@ -11,15 +11,15 @@ gen_sources: sources.txt
ase-1c: gen_sources setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work
cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_1c/work
ase-2c: gen_sources setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work
cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_2c/work
ase-4c: gen_sources setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
cp ../rtl/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work
cp $(RTL_DIR)/fp_cores/altera/*.hex $(ASE_BUILD_DIR)_4c/work
setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
@@ -38,15 +38,15 @@ $(ASE_BUILD_DIR)_4c/Makefile: sources.txt
fpga-1c: gen_sources setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && qsub-synth
cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c
cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_1c
fpga-2c: gen_sources setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && qsub-synth
cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c
cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_2c
fpga-4c: gen_sources setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && qsub-synth
cp ../rtl/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c
cp $(RTL_DIR)/fp_cores/altera/*.hex $(FPGA_BUILD_DIR)_4c
setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
@@ -90,3 +90,5 @@ clean-fpga-2c:
clean-fpga-4c:
rm -rf $(FPGA_BUILD_DIR)_4c sources.txt
clean: clean-ase-1c clean-ase-2c clean-ase-4c clean-fpga-1c clean-fpga-2c clean-fpga-4c
rm sources.txt

4
hw/opae/README
View File

@@ -87,8 +87,8 @@ tar -cvjf trace.fst.tar.bz2 trace.fst run.log
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
# decompress VCD trace
tar -zxvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.gz
tar -xvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.bz2
tar -zxvf vortex.vcd.tar.gz
tar -xvf vortex.vcd.tar.bz2
# launch Gtkwave
gtkwave ./build_ase_1c/work/vortex.vcd &

131
hw/opae/VX_avs_wrapper.v
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@@ -1,131 +0,0 @@
`include "VX_define.vh"
module VX_avs_wrapper #(
parameter AVS_DATAW = 1,
parameter AVS_ADDRW = 1,
parameter AVS_BURSTW = 1,
parameter AVS_BANKS = 1,
parameter REQ_TAGW = 1,
parameter RD_QUEUE_SIZE = 1,
parameter AVS_BYTEENW = (AVS_DATAW / 8),
parameter RD_QUEUE_ADDRW= $clog2(RD_QUEUE_SIZE+1),
parameter AVS_BANKS_BITS= $clog2(AVS_BANKS)
) (
input wire clk,
input wire reset,
// AVS bus
output wire [AVS_DATAW-1:0] avs_writedata,
input wire [AVS_DATAW-1:0] avs_readdata,
output wire [AVS_ADDRW-1:0] avs_address,
input wire avs_waitrequest,
output wire avs_write,
output wire avs_read,
output wire [AVS_BYTEENW-1:0] avs_byteenable,
output wire [AVS_BURSTW-1:0] avs_burstcount,
input avs_readdatavalid,
output wire [AVS_BANKS_BITS-1:0] avs_bankselect,
// DRAM request
input wire dram_req_valid,
input wire dram_req_rw,
input wire [AVS_BYTEENW-1:0] dram_req_byteen,
input wire [AVS_ADDRW-1:0] dram_req_addr,
input wire [AVS_DATAW-1:0] dram_req_data,
input wire [REQ_TAGW-1:0] dram_req_tag,
output wire dram_req_ready,
// DRAM response
output wire dram_rsp_valid,
output wire [AVS_DATAW-1:0] dram_rsp_data,
output wire [REQ_TAGW-1:0] dram_rsp_tag,
input wire dram_rsp_ready
);
reg [AVS_BANKS_BITS-1:0] avs_bankselect_r;
reg [AVS_BURSTW-1:0] avs_burstcount_r;
wire avs_reqq_push = dram_req_valid && dram_req_ready && !dram_req_rw;
wire avs_reqq_pop = dram_rsp_valid && dram_rsp_ready;
wire avs_rspq_push = avs_readdatavalid;
wire avs_rspq_pop = avs_reqq_pop;
wire avs_rspq_empty;
reg [RD_QUEUE_ADDRW-1:0] avs_pending_reads;
wire [RD_QUEUE_ADDRW-1:0] avs_pending_reads_n;
assign avs_pending_reads_n = avs_pending_reads
+ RD_QUEUE_ADDRW'((avs_reqq_push && !avs_rspq_pop) ? 1 :
(avs_rspq_pop && !avs_reqq_push) ? -1 : 0);
always @(posedge clk) begin
if (reset) begin
avs_burstcount_r <= 1;
avs_bankselect_r <= 0;
avs_pending_reads <= 0;
end else begin
avs_pending_reads <= avs_pending_reads_n;
end
end
VX_generic_queue #(
.DATAW (REQ_TAGW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
) rd_req_queue (
.clk (clk),
.reset (reset),
.push (avs_reqq_push),
.pop (avs_reqq_pop),
.data_in (dram_req_tag),
.data_out (dram_rsp_tag),
`UNUSED_PIN (empty),
`UNUSED_PIN (full),
`UNUSED_PIN (size)
);
VX_generic_queue #(
.DATAW (AVS_DATAW),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (1)
) rd_rsp_queue (
.clk (clk),
.reset (reset),
.push (avs_rspq_push),
.pop (avs_rspq_pop),
.data_in (avs_readdata),
.data_out (dram_rsp_data),
.empty (avs_rspq_empty),
`UNUSED_PIN (full),
`UNUSED_PIN (size)
);
wire rsp_queue_ready = (avs_pending_reads != RD_QUEUE_SIZE);
assign avs_read = dram_req_valid && !dram_req_rw && rsp_queue_ready;
assign avs_write = dram_req_valid && dram_req_rw && rsp_queue_ready;
assign avs_address = dram_req_addr;
assign avs_byteenable = dram_req_byteen;
assign avs_writedata = dram_req_data;
assign dram_req_ready = !avs_waitrequest && rsp_queue_ready;
assign avs_burstcount = avs_burstcount_r;
assign avs_bankselect = avs_bankselect_r;
assign dram_rsp_valid = !avs_rspq_empty;
`ifdef DBG_PRINT_AVS
always @(posedge clk) begin
if (dram_req_valid && dram_req_ready) begin
if (dram_req_rw)
$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, dram_req_data);
else
$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `TO_FULL_ADDR(dram_req_addr), dram_req_byteen, dram_req_tag, avs_pending_reads_n);
end
if (dram_rsp_valid && dram_rsp_ready) begin
$display("%t: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d", $time, dram_rsp_tag, dram_rsp_data, avs_pending_reads_n);
end
end
`endif
endmodule

244
hw/opae/ccip/ccip_if_pkg.sv
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@@ -1,244 +0,0 @@
// Date: 02/2/2016
// Compliant with CCI-P spec v0.71
package ccip_if_pkg;
//=====================================================================
// CCI-P interface defines
//=====================================================================
parameter CCIP_VERSION_NUMBER = 12'h071;
parameter CCIP_CLADDR_WIDTH = 42;
parameter CCIP_CLDATA_WIDTH = 512;
parameter CCIP_MMIOADDR_WIDTH = 16;
parameter CCIP_MMIODATA_WIDTH = 64;
parameter CCIP_TID_WIDTH = 9;
parameter CCIP_MDATA_WIDTH = 16;
// Number of requests that can be accepted after almost full is asserted.
parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8;
parameter CCIP_MMIO_RD_TIMEOUT = 512;
parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset
// Base types
//----------------------------------------------------------------------
typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr;
typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData;
typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr;
typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData;
typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid;
typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata;
typedef logic [1:0] t_ccip_clNum;
typedef logic [2:0] t_ccip_qwIdx;
// Request Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid
eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared
} t_ccip_c0_req;
// Channel 1
typedef enum logic [3:0] {
eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid
eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified
eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY **
eREQ_WRFENCE = 4'h4, // Memory Write Fence
// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY **
eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_req;
// Response Type Encodings
//----------------------------------------------------------------------
// Channel 0
typedef enum logic [3:0] {
eRSP_RDLINE = 4'h0, // Memory Read
eRSP_UMSG = 4'h4 // UMsg received
// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr
} t_ccip_c0_rsp;
// Channel 1
typedef enum logic [3:0] {
eRSP_WRLINE = 4'h0, // Memory Write
eRSP_WRFENCE = 4'h4, // Memory Write Fence
eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY **
} t_ccip_c1_rsp;
//
// Virtual Channel Select
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eVC_VA = 2'b00,
eVC_VL0 = 2'b01,
eVC_VH0 = 2'b10,
eVC_VH1 = 2'b11
} t_ccip_vc;
// Multi-CL Memory Request
//----------------------------------------------------------------------
typedef enum logic [1:0] {
eCL_LEN_1 = 2'b00,
eCL_LEN_2 = 2'b01,
eCL_LEN_4 = 2'b11
} t_ccip_clLen;
//
// Structures for Request and Response headers
//----------------------------------------------------------------------
typedef struct packed {
t_ccip_vc vc_sel;
logic [1:0] rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c0_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c0_ReqMemHdr;
parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2;
t_ccip_vc vc_sel;
logic sop;
logic rsvd1; // reserved, drive 0
t_ccip_clLen cl_len;
t_ccip_c1_req req_type;
logic [5:0] rsvd0; // reserved, drive 0
t_ccip_clAddr address;
t_ccip_mdata mdata;
} t_ccip_c1_ReqMemHdr;
parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr);
typedef struct packed {
logic [5:0] rsvd2; // reserved, drive 0
t_ccip_vc vc_sel;
logic [3:0] rsvd1; // reserved, drive 0
t_ccip_c1_req req_type;
logic [47:0] rsvd0; // reserved, drive 0
t_ccip_mdata mdata;
}t_ccip_c1_ReqFenceHdr;
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic [1:0] rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c0_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c0_RspMemHdr;
parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr);
typedef struct packed {
t_ccip_vc vc_used;
logic rsvd1; // reserved, don't care
logic hit_miss;
logic format;
logic rsvd0; // reserved, don't care
t_ccip_clNum cl_num;
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspMemHdr;
parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr);
typedef struct packed {
logic [7:0] rsvd0; // reserved, don't care
t_ccip_c1_rsp resp_type;
t_ccip_mdata mdata;
} t_ccip_c1_RspFenceHdr;
// Alternate Channel 0 MMIO request from host :
// MMIO requests arrive on the same channel as read responses, sharing
// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set
// the message is an MMIO request and should be processed by casting
// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.
typedef struct packed {
t_ccip_mmioAddr address; // 4B aligned Mmio address
logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B
logic rsvd; // reserved, don't care
t_ccip_tid tid;
} t_ccip_c0_ReqMmioHdr;
typedef struct packed {
t_ccip_tid tid; // Returned back from ReqMmioHdr
} t_ccip_c2_RspMmioHdr;
parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr);
//------------------------------------------------------------------------
// CCI-P Input & Output bus structures
//
// Users are encouraged to use these for AFU development
//------------------------------------------------------------------------
// Channel 0 : Memory Reads
typedef struct packed {
t_ccip_c0_ReqMemHdr hdr; // Request Header
logic valid; // Request Valid
} t_if_ccip_c0_Tx;
// Channel 1 : Memory Writes, Interrupts, CmpXchg
typedef struct packed {
t_ccip_c1_ReqMemHdr hdr; // Request Header
t_ccip_clData data; // Request Data
logic valid; // Request Wr Valid
} t_if_ccip_c1_Tx;
// Channel 2 : MMIO Read response
typedef struct packed {
t_ccip_c2_RspMmioHdr hdr; // Response Header
logic mmioRdValid; // Response Read Valid
t_ccip_mmioData data; // Response Data
} t_if_ccip_c2_Tx;
// Wrap all Tx channels
typedef struct packed {
t_if_ccip_c0_Tx c0;
t_if_ccip_c1_Tx c1;
t_if_ccip_c2_Tx c2;
} t_if_ccip_Tx;
// Channel 0: Memory Read response, MMIO Request
typedef struct packed {
t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header
t_ccip_clData data; // Rd Data / MMIO req Data
// Only one of valid, mmioRdValid and mmioWrValid may be set
// in a cycle. When either mmioRdValid or mmioWrValid are true
// the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr
// above.
logic rspValid; // Rd Response Valid
logic mmioRdValid; // MMIO Read Valid
logic mmioWrValid; // MMIO Write Valid
} t_if_ccip_c0_Rx;
// Channel 1: Memory Writes
typedef struct packed {
t_ccip_c1_RspMemHdr hdr; // Response Header
logic rspValid; // Response Valid
} t_if_ccip_c1_Rx;
// Wrap all channels
typedef struct packed {
logic c0TxAlmFull; // C0 Request Channel Almost Full
logic c1TxAlmFull; // C1 Request Channel Almost Full
t_if_ccip_c0_Rx c0;
t_if_ccip_c1_Rx c1;
} t_if_ccip_Rx;
typedef union packed {
t_ccip_c0_RspMemHdr rspMemHdr;
t_ccip_c0_ReqMmioHdr reqMmioHdr;
} t_if_ccip_c0_RxHdr;
endpackage

61
hw/opae/ccip/local_mem_cfg_pkg.sv
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@@ -1,61 +0,0 @@
//
// Copyright (c) 2017, Intel Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//`include "platform_afu_top_config.vh"
`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY
package local_mem_cfg_pkg;
parameter LOCAL_MEM_VERSION_NUMBER = 1;
parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH;
parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH;
parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH;
// Number of bytes in a data line
parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8;
// Base types
// --------------------------------------------------------------------
typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr;
typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data;
typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt;
// Byte-level mask of a data line
typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask;
endpackage // local_mem_cfg_pkg
`endif // PLATFORM_PROVIDES_LOCAL_MEMORY

48
hw/opae/ccip_interface_reg.sv
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@@ -1,48 +0,0 @@
// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
// Register all interface signals
import ccip_if_pkg::*;
module ccip_interface_reg(
// CCI-P Clocks and Resets
input logic pClk, // 400MHz - CC-P clock domain. Primary Clock
input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset
input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State
input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected
// Interface structures
input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port
input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port
output logic pck_cp2af_softReset_T1,
output logic [1:0] pck_cp2af_pwrState_T1,
output logic pck_cp2af_error_T1,
output t_if_ccip_Rx pck_cp2af_sRx_T1,
output t_if_ccip_Tx pck_af2cp_sTx_T1
);
(* preserve *) logic pck_cp2af_softReset_T0_q;
(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q;
(* preserve *) logic pck_cp2af_error_T0_q;
(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q;
(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q;
always@(posedge pClk)
begin
pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0;
pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0;
pck_cp2af_error_T0_q <= pck_cp2af_error_T0;
pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0;
pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0;
end
always_comb
begin
pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q;
pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q;
pck_cp2af_error_T1 = pck_cp2af_error_T0_q;
pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q;
pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q;
end
endmodule

167
hw/opae/ccip_std_afu.sv
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@@ -1,167 +0,0 @@
// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex
// Top Level Vortex Driver
// To be done:
// Check how to run this with OPAE. Looks like setup issue
`include "platform_if.vh"
import local_mem_cfg_pkg::*;
module ccip_std_afu #(
parameter NUM_LOCAL_MEM_BANKS = 2
) (
// CCI-P Clocks and Resets
input logic pClk, // Primary CCI-P interface clock.
input logic pClkDiv2, // Aligned, pClk divided by 2.
input logic pClkDiv4, // Aligned, pClk divided by 4.
input logic uClk_usr, // User clock domain. Refer to clock programming guide.
input logic uClk_usrDiv2, // Aligned, user clock divided by 2.
input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
input logic pck_cp2af_error, // CCI-P Protocol Error Detected
// CCI-P structures
input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port
// Local memory interface
avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS]
);
// ====================================================================
// Pick the proper clk and reset, as chosen by the AFU's JSON file
// ====================================================================
// The platform may transform the CCI-P clock from pClk to a clock
// chosen in the AFU's JSON file.
logic clk;
assign clk = `PLATFORM_PARAM_CCI_P_CLOCK;
logic reset;
assign reset = `PLATFORM_PARAM_CCI_P_RESET;
// ====================================================================
// Register signals at interface before consuming them
// ====================================================================
(* noprune *) logic [1:0] cp2af_pwrState_T1;
(* noprune *) logic cp2af_error_T1;
logic reset_T1;
t_if_ccip_Rx cp2af_sRx_T1;
t_if_ccip_Tx af2cp_sTx_T0;
ccip_interface_reg inst_green_ccip_interface_reg
(
.pClk (clk),
.pck_cp2af_softReset_T0 (reset),
.pck_cp2af_pwrState_T0 (pck_cp2af_pwrState),
.pck_cp2af_error_T0 (pck_cp2af_error),
.pck_cp2af_sRx_T0 (pck_cp2af_sRx),
.pck_af2cp_sTx_T0 (af2cp_sTx_T0),
.pck_cp2af_softReset_T1 (reset_T1),
.pck_cp2af_pwrState_T1 (cp2af_pwrState_T1),
.pck_cp2af_error_T1 (cp2af_error_T1),
.pck_cp2af_sRx_T1 (cp2af_sRx_T1),
.pck_af2cp_sTx_T1 (pck_af2cp_sTx)
);
// ====================================================================
// User AFU goes here
// ====================================================================
//
// vortex_afu depends on CCI-P and local memory being in the same
// clock domain. This is accomplished by choosing a common clock
// in the AFU's JSON description. The platform instantiates clock-
// crossing shims automatically, as needed.
//
//
// Memory banks are used very simply here. Only bank is active at
// a time, selected by mem_bank_select. mem_bank_select is set
// by a CSR from the host.
//
t_local_mem_byte_mask avs_byteenable;
logic avs_waitrequest;
t_local_mem_data avs_readdata;
logic avs_readdatavalid;
t_local_mem_burst_cnt avs_burstcount;
t_local_mem_data avs_writedata;
t_local_mem_addr avs_address;
logic avs_write;
logic avs_read;
// choose which memory bank to test
logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select;
vortex_afu #(
.NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS)
) afu (
.clk (clk),
.reset (reset_T1),
.avs_writedata (avs_writedata),
.avs_readdata (avs_readdata),
.avs_address (avs_address),
.avs_waitrequest (avs_waitrequest),
.avs_write (avs_write),
.avs_read (avs_read),
.avs_byteenable (avs_byteenable),
.avs_burstcount (avs_burstcount),
.avs_readdatavalid (avs_readdatavalid),
.mem_bank_select (mem_bank_select),
.cp2af_sRxPort (cp2af_sRx_T1),
.af2cp_sTxPort (af2cp_sTx_T0)
);
//
// Export the local memory interface signals as vectors so that bank
// selection can use array syntax.
//
logic avs_waitrequest_v[NUM_LOCAL_MEM_BANKS];
t_local_mem_data avs_readdata_v[NUM_LOCAL_MEM_BANKS];
logic avs_readdatavalid_v[NUM_LOCAL_MEM_BANKS];
genvar b;
generate
for (b = 0; b < NUM_LOCAL_MEM_BANKS; b = b + 1)
begin : lmb
always_comb
begin
// Local memory to AFU signals
avs_waitrequest_v[b] = local_mem[b].waitrequest;
avs_readdata_v[b] = local_mem[b].readdata;
avs_readdatavalid_v[b] = local_mem[b].readdatavalid;
// Replicate address and write data to all banks. Only
// the request signals have to be bank-specific.
local_mem[b].burstcount = avs_burstcount;
local_mem[b].writedata = avs_writedata;
local_mem[b].address = avs_address;
local_mem[b].byteenable = avs_byteenable;
// Request a write to this bank?
local_mem[b].write = avs_write &&
($bits(mem_bank_select)'(b) == mem_bank_select);
// Request a read from this bank?
local_mem[b].read = avs_read &&
($bits(mem_bank_select)'(b) == mem_bank_select);
end
end
endgenerate
assign avs_waitrequest = avs_waitrequest_v[mem_bank_select];
assign avs_readdata = avs_readdata_v[mem_bank_select];
assign avs_readdatavalid = avs_readdatavalid_v[mem_bank_select];
endmodule

7
hw/opae/gen_sources.sh
View File

@@ -1,7 +1,10 @@
#!/bin/bash
dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl ../rtl/fp_cores/fpnew/src/common_cells/include ../rtl/fp_cores ../rtl/fp_cores/altera'
exclude_list='VX_fpnew.v'
rtl_dir="../rtl"
dir_list="$rtl_dir/libs $rtl_dir/cache $rtl_dir/interfaces $rtl_dir $rtl_dir/fp_cores/fpnew/src/common_cells/include $rtl_dir/fp_cores $rtl_dir/fp_cores/altera $rtl_dir/afu"
exclude_list="VX_fpnew.v"
# read design sources
for dir in $dir_list; do

97
hw/opae/opae_setup.sh
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@@ -1,97 +0,0 @@
## Required tools
# gcc (>4.9)
# libjson
# python
# Quartus
# RTL Simulator (VCS or ModelSim or QuestaSim)
## Download OPAE SDK from https://github.com/OPAE/opae-sdk/archive/1.4.0-1.tar.gz
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/
## Update the following file based on /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
# ./opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
###################################################################################################
################################### TO BE DONE EVERY TIME #########################################
###################################################################################################
## Change the shell to bash before running
bash
## Setup Environment
## Running the default script results in multiple versions of libcurl during cmake.
#source /nethome/achawda6/specialProblem/rg_intel_fpga_end_19.3.sh
source /tools/reconfig/intel/19.3/rg_intel_fpga_end_19.3.sh
## Setup the variables for using the Quartus modelsim
source /nethome/achawda6/specialProblem/modelsim_env.sh
## Run this to setup the environment variables
source /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/ase_setup_template.sh
## gcc version should be greater than 4.9 to support c++14
source /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/env_check.sh
export PATH=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall/bin:${PATH}
export FPGA_BBB_CCI_SRC=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
####################################################################################################
## Setup OPAE
mkdir mybuild
cd mybuild
## Update the directory path where you want to install OPAE
cmake .. -DBUILD_ASE=1 -DCMAKE_INSTALL_PREFIX=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall
make
make install
## Setup ASE
## Add the installed OPAE path in PATH
export PATH=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall/bin:${PATH}
## Use this version of HDL files
/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/scripts/afu_sim_setup --sources=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/libopae/plugins/ase/rtl/sources_ase_server.txt run1Build
cd run1Build/
python scripts/ipc_clean.py
## Running Sample
## Download opae-bbb from https://github.com/OPAE/intel-fpga-bbb
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1
git clone https://github.com/OPAE/intel-fpga-bbb
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
mkdir mybuild
cd mybuild
cmake .. -DCMAKE_INSTALL_PREFIX=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/mybuild/opaeInstall
make
make install
export FPGA_BBB_CCI_SRC=/nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb
## Running hello world
cd /nethome/achawda6/specialProblem/opae-sdk-1.4.0-1/intel-fpga-bbb/samples/tutorial/01_hello_world
afu_sim_setup --source hw/rtl/sources.txt build_sim
cd build_sim
## Update libstdc++6 if it errors out
make
make sim

8
hw/opae/set_env.sh
View File

@@ -1,8 +0,0 @@
#!/bin/bash
source /tools/reconfig/intel/19.3/rg_intel_fpga_end_19.3.sh
export PATH=/tools/opae/1.4.0/bin:/tools/reconfig/intel/19.3/modelsim_ase/bin:$PATH
export LD_LIBRARY_PATH=/tools/opae/1.4.0/lib:$PATH
export QUARTUS_HOME=$QUARTUS_ROOTDIR
export MTI_HOME=/tools/reconfig/intel/19.3/modelsim_ase
export FPGA_FAMILY=arria10

4
hw/opae/sources_1c.txt
View File

@@ -21,9 +21,5 @@
vortex_afu.json
QI:vortex_afu.qsf
ccip_interface_reg.sv
ccip_std_afu.sv
VX_avs_wrapper.v
vortex_afu.sv
C:sources.txt

4
hw/opae/sources_2c.txt
View File

@@ -6,9 +6,5 @@
vortex_afu.json
QI:vortex_afu.qsf
ccip_interface_reg.sv
ccip_std_afu.sv
VX_avs_wrapper.v
vortex_afu.sv
C:sources.txt

4
hw/opae/sources_4c.txt
View File

@@ -6,9 +6,5 @@
vortex_afu.json
QI:vortex_afu.qsf
ccip_interface_reg.sv
ccip_std_afu.sv
VX_avs_wrapper.v
vortex_afu.sv
C:sources.txt

1091
hw/opae/vortex_afu.sv
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File diff suppressed because it is too large Load Diff

37
hw/opae/vortex_afu.vh
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@@ -1,37 +0,0 @@
`ifndef __VORTEX_AFU__
`define __VORTEX_AFU__
`include "ccip_if_pkg.sv"
`define PLATFORM_PROVIDES_LOCAL_MEMORY
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
`include "local_mem_cfg_pkg.sv"
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c
`define AFU_IMAGE_CMD_CLFLUSH 4
`define AFU_IMAGE_CMD_CSR_READ 5
`define AFU_IMAGE_CMD_CSR_WRITE 6
`define AFU_IMAGE_CMD_MEM_READ 1
`define AFU_IMAGE_CMD_MEM_WRITE 2
`define AFU_IMAGE_CMD_RUN 3
`define AFU_IMAGE_MMIO_CMD_TYPE 10
`define AFU_IMAGE_MMIO_CSR_CORE 24
`define AFU_IMAGE_MMIO_CSR_ADDR 26
`define AFU_IMAGE_MMIO_CSR_DATA 28
`define AFU_IMAGE_MMIO_CSR_READ 30
`define AFU_IMAGE_MMIO_DATA_SIZE 16
`define AFU_IMAGE_MMIO_IO_ADDR 12
`define AFU_IMAGE_MMIO_MEM_ADDR 14
`define AFU_IMAGE_MMIO_SCOPE_READ 20
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
`define AFU_IMAGE_MMIO_STATUS 18
`define AFU_IMAGE_POWER 0
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
`endif