rtl multicore fix
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@@ -15,11 +15,9 @@ module VX_generic_stack #(
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reg [DEPTH - 1:0] ptr;
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reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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ptr <= 0;
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for (i = 0; i < (1 << DEPTH); i=i+1) stack[i] <= 0;
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end else if (push) begin
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stack[ptr] <= q1;
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stack[ptr+1] <= q2;
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