wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

register file refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-12-05 01:40:50 -08:00
parent 478d971389
commit 13a5370254
33 changed files with 524 additions and 605 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
hw/rtl/interfaces/VX_csr_pipe_req_if.v Normal file
View File

@@ -0,0 +1,24 @@
`ifndef VX_CSR_PIPE_REQ_IF
`define VX_CSR_PIPE_REQ_IF
`include "VX_define.vh"
interface VX_csr_pipe_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] csr_mask;
wire [`NR_BITS-1:0] rd;
wire wb;
wire is_io;
wire ready;
endinterface
`endif

5
hw/rtl/interfaces/VX_csr_req_if.v
View File

@@ -12,10 +12,11 @@ interface VX_csr_req_if ();
wire [31:0] PC;
wire [`CSR_BITS-1:0] op_type;
wire [`CSR_ADDR_BITS-1:0] csr_addr;
wire [31:0] csr_mask;
wire [31:0] rs1_data;
wire rs2_is_imm;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rd;
wire wb;
wire is_io;
wire ready;

3
hw/rtl/interfaces/VX_decode_if.v
View File

@@ -20,8 +20,7 @@ interface VX_decode_if ();
wire [`NR_BITS-1:0] rs3;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire use_rs3;
wire rs2_is_imm;
wire [`NUM_REGS-1:0] used_regs;
wire ready;

16
hw/rtl/interfaces/VX_gpr_req_if.v
View File

@@ -4,17 +4,11 @@
`include "VX_define.vh"
interface VX_gpr_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire use_rs3;
wire ready;
wire [`NW_BITS-1:0] wid;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
endinterface

8
hw/rtl/interfaces/VX_gpr_rsp_if.v
View File

@@ -4,17 +4,11 @@
`include "VX_define.vh"
interface VX_gpr_rsp_if ();
wire valid;
`IGNORE_WARNINGS_BEGIN
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
`IGNORE_WARNINGS_END
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire ready;
endinterface
`endif