refactoring fixes

hw/simulate/ram.h

@@ -0,0 +1,212 @@
+#pragma once
+
+#include <stdio.h>
+#include <stdint.h>
+
+class RAM;
+
+uint32_t hti(char);
+uint32_t hToI(const char *, uint32_t);
+void loadHexImpl(const char *, RAM *);
+
+class RAM {
+public:
+  uint8_t *mem[1 << 12];
+
+  RAM() {
+    for (uint32_t i = 0; i < (1 << 12); i++)
+      mem[i] = NULL;
+  }
+  ~RAM() {
+    for (uint32_t i = 0; i < (1 << 12); i++)
+      if (mem[i])
+        delete[] mem[i];
+  }
+
+  size_t size() const {
+    return (1ull << 32);
+  }
+
+  void clear() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      if (mem[i]) {
+        delete mem[i];
+        mem[i] = NULL;
+      }
+    }
+  }
+
+  uint8_t *get(uint32_t address) {
+
+    if (mem[address >> 20] == NULL) {
+      uint8_t *ptr = new uint8_t[1024 * 1024];
+      for (uint32_t i = 0; i < 1024 * 1024; i += 4) {
+        ptr[i + 0] = 0x00;
+        ptr[i + 1] = 0x00;
+        ptr[i + 2] = 0x00;
+        ptr[i + 3] = 0x00;
+      }
+      mem[address >> 20] = ptr;
+    }
+    return &mem[address >> 20][address & 0xFFFFF];
+  }
+
+  void read(uint32_t address, uint32_t length, uint8_t *data) {
+    for (unsigned i = 0; i < length; i++) {
+      data[i] = (*this)[address + i];
+    }
+  }
+
+  void write(uint32_t address, uint32_t length, uint8_t *data) {
+    for (unsigned i = 0; i < length; i++) {
+      (*this)[address + i] = data[i];
+    }
+  }
+
+  void getBlock(uint32_t address, uint8_t *data) {
+    uint32_t block_number = address & 0xffffff00; // To zero out block offset
+    uint32_t bytes_num = 256;
+
+    this->read(block_number, bytes_num, data);
+  }
+
+  void getWord(uint32_t address, uint32_t *data) {
+    data[0] = 0;
+
+    uint8_t first = *get(address + 0);
+    uint8_t second = *get(address + 1);
+    uint8_t third = *get(address + 2);
+    uint8_t fourth = *get(address + 3);
+
+    data[0] = (data[0] << 0) | fourth;
+    data[0] = (data[0] << 8) | third;
+    data[0] = (data[0] << 8) | second;
+    data[0] = (data[0] << 8) | first;
+  }
+
+  void writeWord(uint32_t address, uint32_t *data) {
+    uint32_t data_to_write = *data;
+
+    uint32_t byte_mask = 0xFF;
+
+    for (int i = 0; i < 4; i++) {
+      (*this)[address + i] = data_to_write & byte_mask;
+      data_to_write = data_to_write >> 8;
+    }
+  }
+
+  void writeHalf(uint32_t address, uint32_t *data) {
+    uint32_t data_to_write = *data;
+
+    uint32_t byte_mask = 0xFF;
+
+    for (int i = 0; i < 2; i++) {
+      (*this)[address + i] = data_to_write & byte_mask;
+      data_to_write = data_to_write >> 8;
+    }
+  }
+
+  void writeByte(uint32_t address, uint32_t *data) {
+    uint32_t data_to_write = *data;
+
+    uint32_t byte_mask = 0xFF;
+
+    (*this)[address] = data_to_write & byte_mask;
+    data_to_write = data_to_write >> 8;
+  }
+
+  uint8_t &operator[](uint32_t address) {
+    return *get(address);
+  }
+};
+
+// MEMORY UTILS
+
+inline uint32_t hti(char c) {
+  if (c >= 'A' && c <= 'F')
+    return c - 'A' + 10;
+  if (c >= 'a' && c <= 'f')
+    return c - 'a' + 10;
+  return c - '0';
+}
+
+inline uint32_t hToI(const char *c, uint32_t size) {
+  uint32_t value = 0;
+  for (uint32_t i = 0; i < size; i++) {
+    value += hti(c[i]) << ((size - i - 1) * 4);
+  }
+  return value;
+}
+
+inline void loadHexImpl(const char *path, RAM *mem) {
+  mem->clear();
+  FILE *fp = fopen(path, "r");
+  if (fp == 0) {
+    printf("Path not found %s\n", path);
+    return;
+    // std::cout << path << " not found" << std::endl;
+  }
+  //Preload 0x0 <-> 0x80000000 jumps
+  ((uint32_t *)mem->get(0))[1] = 0xf1401073;
+
+  ((uint32_t *)mem->get(0))[2] = 0x30101073;
+
+  ((uint32_t *)mem->get(0))[3] = 0x800000b7;
+  ((uint32_t *)mem->get(0))[4] = 0x000080e7;
+
+  ((uint32_t *)mem->get(0x80000000))[0] = 0x00000097;
+
+  ((uint32_t *)mem->get(0xb0000000))[0] = 0x01C02023;
+  // F00FFF10
+  ((uint32_t *)mem->get(0xf00fff10))[0] = 0x12345678;
+
+  fseek(fp, 0, SEEK_END);
+  uint32_t size = ftell(fp);
+  fseek(fp, 0, SEEK_SET);
+  char *content = new char[size];
+  fread(content, 1, size, fp);
+
+  int offset = 0;
+  char *line = content;
+  // std::cout << "WHTA\n";
+  while (1) {
+    if (line[0] == ':') {
+      uint32_t byteCount = hToI(line + 1, 2);
+      uint32_t nextAddr = hToI(line + 3, 4) + offset;
+      uint32_t key = hToI(line + 7, 2);
+      switch (key) {
+      case 0:
+        for (uint32_t i = 0; i < byteCount; i++) {
+
+          unsigned add = nextAddr + i;
+
+          *(mem->get(add)) = hToI(line + 9 + i * 2, 2);
+        }
+        break;
+      case 2:
+        //              cout << offset << endl;
+        offset = hToI(line + 9, 4) << 4;
+        break;
+      case 4:
+        //              cout << offset << endl;
+        offset = hToI(line + 9, 4) << 16;
+        break;
+      default:
+        //              cout << "??? " << key << endl;
+        break;
+      }
+    }
+
+    while (*line != '\n' && size != 0) {
+      line++;
+      size--;
+    }
+    if (size <= 1)
+      break;
+    line++;
+    size--;
+  }
+
+  if (content)
+    delete[] content;
+}

hw/simulate/simulator.cpp

@@ -0,0 +1,388 @@
+#include "simulator.h"
+#include <iostream>
+#include <iomanip>
+
+Simulator::Simulator(RAM *ram)
+    : total_cycles_(0)
+    , dram_stalled_(false)
+    , I_dram_stalled_(false) {
+  ram_ = ram;
+
+#ifdef USE_MULTICORE
+  vortex_ = new VVortex_Socket();
+#else
+  vortex_ = new VVortex();
+#endif
+
+#ifdef VCD_OUTPUT
+  Verilated::traceEverOn(true);
+  trace_ = new VerilatedVcdC;
+  vortex_->trace(trace_, 99);
+  trace_->open("trace.vcd");
+#endif  
+}
+
+Simulator::~Simulator() {
+#ifdef VCD_OUTPUT
+  trace_->close();
+#endif
+  delete vortex_;
+}
+
+void Simulator::print_stats(std::ostream& out) {
+  out << std::left;
+  out << std::setw(24) << "# of total cycles:" << std::dec << total_cycles_ << std::endl;
+}
+
+#ifndef USE_MULTICORE
+
+void Simulator::ibus_driver() {
+  // Iterate through each element, and get pop index
+  int dequeue_index = -1;
+  bool dequeue_valid = false;
+  for (int i = 0; i < I_dram_req_vec_.size(); i++) {
+    if (I_dram_req_vec_[i].cycles_left > 0) {
+      I_dram_req_vec_[i].cycles_left -= 1;
+    }
+
+    if ((I_dram_req_vec_[i].cycles_left == 0) && (!dequeue_valid)) {
+      dequeue_index = i;
+      dequeue_valid = true;
+    }
+  }
+
+  if (vortex_->I_dram_req && !I_dram_stalled_) {
+    // std::cout << "Icache Dram Request received!\n";
+    if (vortex_->I_dram_req_read) {
+      // std::cout << "Icache Dram Request is read!\n";
+      // Need to add an element
+      dram_req_t dram_req;
+      dram_req.cycles_left = DRAM_LATENCY;
+      dram_req.data_length = vortex_->I_dram_req_size / 4;
+      dram_req.base_addr = vortex_->I_dram_req_addr;
+      dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
+
+      for (int i = 0; i < dram_req.data_length; i++) {
+        unsigned curr_addr = dram_req.base_addr + (i * 4);
+        unsigned data_rd;
+        ram_->getWord(curr_addr, &data_rd);
+        dram_req.data[i] = data_rd;
+      }
+      // std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
+      I_dram_req_vec_.push_back(dram_req);
+    }
+
+    if (vortex_->I_dram_req_write) {
+      unsigned base_addr = vortex_->I_dram_req_addr;
+      unsigned data_length = vortex_->I_dram_req_size / 4;
+
+      for (int i = 0; i < data_length; i++) {
+        unsigned curr_addr = base_addr + (i * 4);
+        unsigned data_wr = vortex_->I_dram_req_data[i];
+        ram_->writeWord(curr_addr, &data_wr);
+      }
+    }
+  }
+
+  if (vortex_->I_dram_fill_accept && dequeue_valid) {
+    // std::cout << "Icache Dram Response Sending...!\n";
+
+    vortex_->I_dram_fill_rsp = 1;
+    vortex_->I_dram_fill_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr;
+    // std::cout << "Fill Rsp -> Addr: " << std::hex << (I_dram_req_vec_[dequeue_index].base_addr) << std::dec << "\n";
+
+    for (int i = 0; i < I_dram_req_vec_[dequeue_index].data_length; i++) {
+      vortex_->I_dram_fill_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i];
+    }
+    free(I_dram_req_vec_[dequeue_index].data);
+
+    I_dram_req_vec_.erase(I_dram_req_vec_.begin() + dequeue_index);
+  } else {
+    vortex_->I_dram_fill_rsp = 0;
+    vortex_->I_dram_fill_rsp_addr = 0;
+  }
+
+#ifdef ENABLE_DRAM_STALLS
+  I_dram_stalled_ = false;
+  if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) { 
+    I_dram_stalled_ = true;
+  } else
+  if (I_dram_req_vec_.size() >= DRAM_RQ_SIZE) {
+    I_dram_stalled_ = true;
+  }  
+#endif
+
+  vortex_->dram_req_delay = I_dram_stalled_;
+}
+
+#endif
+
+void Simulator::dbus_driver() {
+  // Iterate through each element, and get pop index
+  int dequeue_index = -1;
+  bool dequeue_valid = false;
+  for (int i = 0; i < dram_req_vec_.size(); i++) {
+    if (dram_req_vec_[i].cycles_left > 0) {
+      dram_req_vec_[i].cycles_left -= 1;
+    }
+
+    if ((dram_req_vec_[i].cycles_left == 0) && (!dequeue_valid)) {
+      dequeue_index = i;
+      dequeue_valid = true;
+    }
+  }
+
+#ifdef ENABLE_DRAM_STALLS
+  dram_stalled_ = false;
+  if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) { 
+    dram_stalled_ = true;
+  } else
+  if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
+    dram_stalled_ = true;
+  }  
+#endif
+
+#ifdef USE_MULTICORE
+
+  if (vortex_->out_dram_req && !dram_stalled_) {
+    if (vortex_->out_dram_req_read) {
+      // Need to add an element
+      dram_req_t dram_req;
+      dram_req.cycles_left = DRAM_LATENCY;
+      dram_req.data_length = vortex_->out_dram_req_size / 4;
+      dram_req.base_addr = vortex_->out_dram_req_addr;
+      dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
+
+      for (int i = 0; i < dram_req.data_length; i++) {
+        unsigned curr_addr = dram_req.base_addr + (i * 4);
+        unsigned data_rd;
+        ram_->getWord(curr_addr, &data_rd);
+        dram_req.data[i] = data_rd;
+      }
+      dram_req_vec_.push_back(dram_req);
+    }
+
+    if (vortex_->out_dram_req_write) {
+      unsigned base_addr = vortex_->out_dram_req_addr;
+      unsigned data_length = vortex_->out_dram_req_size / 4;
+
+      for (int i = 0; i < data_length; i++) {
+        unsigned curr_addr = base_addr + (i * 4);
+        unsigned data_wr = vortex_->out_dram_req_data[i];
+        ram_->writeWord(curr_addr, &data_wr);
+      }
+    }
+  }
+
+  if (vortex_->out_dram_fill_accept && dequeue_valid) {
+    vortex_->out_dram_fill_rsp = 1;
+    vortex_->out_dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
+
+    for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) {
+      vortex_->out_dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
+    }
+    free(dram_req_vec_[dequeue_index].data);
+
+    dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
+  } else {
+    vortex_->out_dram_fill_rsp = 0;
+    vortex_->out_dram_fill_rsp_addr = 0;
+  }
+
+#else
+
+  if (vortex_->dram_req && !dram_stalled_) {
+    if (vortex_->dram_req_read) {
+      // Need to add an element
+      dram_req_t dram_req;
+      dram_req.cycles_left = DRAM_LATENCY;
+      dram_req.data_length = vortex_->dram_req_size / 4;
+      dram_req.base_addr = vortex_->dram_req_addr;
+      dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
+
+      for (int i = 0; i < dram_req.data_length; i++) {
+        unsigned curr_addr = dram_req.base_addr + (i * 4);
+        unsigned data_rd;
+        ram_->getWord(curr_addr, &data_rd);
+        dram_req.data[i] = data_rd;
+      }
+      dram_req_vec_.push_back(dram_req);
+    }
+
+    if (vortex_->dram_req_write) {
+      unsigned base_addr = vortex_->dram_req_addr;
+      unsigned data_length = vortex_->dram_req_size / 4;
+
+      for (int i = 0; i < data_length; i++) {
+        unsigned curr_addr = base_addr + (i * 4);
+        unsigned data_wr = vortex_->dram_req_data[i];
+        ram_->writeWord(curr_addr, &data_wr);
+      }
+    }
+  }
+
+  if (vortex_->dram_fill_accept && dequeue_valid) {
+    vortex_->dram_fill_rsp = 1;
+    vortex_->dram_fill_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
+
+    for (int i = 0; i < dram_req_vec_[dequeue_index].data_length; i++) {
+      vortex_->dram_fill_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
+    }
+    free(dram_req_vec_[dequeue_index].data);
+
+    dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
+  } else {
+    vortex_->dram_fill_rsp = 0;
+    vortex_->dram_fill_rsp_addr = 0;
+  }
+  
+#endif
+
+#ifdef USE_MULTICORE
+  vortex_->out_dram_req_delay = dram_stalled_;
+#else
+  vortex_->dram_req_delay = dram_stalled_;
+#endif
+}
+
+void Simulator::io_handler() {
+#ifdef USE_MULTICORE
+  bool io_valid = false;
+  for (int c = 0; c < vortex_->number_cores; c++) {
+    if (vortex_->io_valid[c]) {
+      uint32_t data_write = (uint32_t)vortex_->io_data[c];
+      char c = (char)data_write;
+      std::cerr << c;      
+      io_valid = true;
+    }
+  }
+  if (io_valid) {
+    std::cout << std::flush;
+  }
+#else
+  if (vortex_->io_valid) {
+    uint32_t data_write = (uint32_t)vortex_->io_data;
+    char c = (char)data_write;
+    std::cerr << c;
+    std::cout << std::flush;
+  }
+#endif
+}
+
+void Simulator::reset() {  
+  vortex_->reset = 1;
+  this->step();
+  vortex_->reset = 0;
+}
+
+void Simulator::step() {
+  vortex_->clk = 0;
+  vortex_->eval();
+
+#ifdef VCD_OUTPUT
+  trace_->dump(2 * total_cycles_ + 0);
+#endif
+
+  vortex_->clk = 1;
+  vortex_->eval();
+
+#ifndef USE_MULTICORE
+  ibus_driver();
+#endif
+
+  dbus_driver();
+  io_handler();
+
+#ifdef VCD_OUTPUT
+  trace_->dump(2 * total_cycles_ + 1);
+#endif
+
+  ++total_cycles_;
+}
+
+void Simulator::wait(uint32_t cycles) {
+  for (int i = 0; i < cycles; ++i) {
+    this->step();
+  }
+}
+
+bool Simulator::is_busy() {
+  return (0 == vortex_->out_ebreak);
+}
+
+void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
+  // align address to LLC block boundaries
+  auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * (mem_addr / GLOBAL_BLOCK_SIZE_BYTES);
+  auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
+
+#ifdef USE_MULTICORE
+  // submit snoop requests for the needed blocks
+  vortex_->llc_snp_req_addr = aligned_addr_start;
+  vortex_->llc_snp_req = false;
+  for (;;) {
+    this->step();
+    if (vortex_->llc_snp_req) {
+      vortex_->llc_snp_req = false;
+      if (vortex_->llc_snp_req_addr >= aligned_addr_end)
+        break;
+      vortex_->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
+    }    
+    if (!vortex_->llc_snp_req_delay) {
+      vortex_->llc_snp_req = true;      
+    }
+  }
+#else
+  // submit snoop requests for the needed blocks
+  vortex_->snp_req_addr = aligned_addr_start;
+  vortex_->snp_req = false;
+  for (;;) {
+    this->step();
+    if (vortex_->snp_req) {
+      vortex_->snp_req = false;
+      if (vortex_->snp_req_addr >= aligned_addr_end)
+        break;
+      vortex_->snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
+    }    
+    if (!vortex_->snp_req_delay) {
+      vortex_->snp_req = true;      
+    }
+  }
+#endif
+}
+
+void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
+  printf("[sim] total cycles: %lld\n", this->total_cycles_);
+
+  // send snoops for L1 flush
+  this->send_snoops(mem_addr, size);
+  this->wait(PIPELINE_FLUSH_LATENCY);
+
+// #if NUMBER_CORES != 1
+  // send snoops for L2 flush
+  // this->send_snoops(mem_addr, size);
+  // this->wait(PIPELINE_FLUSH_LATENCY);
+// #endif
+
+}
+
+bool Simulator::run() {
+  // reset the device
+  this->reset();
+
+  // execute program
+  while (!vortex_->out_ebreak) {
+    this->step();
+  }
+
+  // wait 5 cycles to flush the pipeline
+  this->wait(5);
+
+#ifdef USE_MULTICORE
+  int status = 0;
+#else
+  // check riscv-tests PASSED/FAILED status
+  int status = (int)vortex_->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
+#endif
+
+  return (status == 1);
+}

hw/simulate/simulator.h

@@ -0,0 +1,73 @@
+#pragma once
+
+#ifdef USE_MULTICORE
+#include "VVortex_Socket.h"
+#include "VVortex_Socket__Syms.h"
+#else
+#include "VVortex.h"
+#include "VVortex__Syms.h"
+#endif
+#include "verilated.h"
+
+#ifdef VCD_OUTPUT
+#include <verilated_vcd_c.h>
+#endif
+
+#include "VX_define.h"
+#include "ram.h"
+
+#include <ostream>
+#include <vector>
+
+#define ENABLE_DRAM_STALLS
+#define DRAM_LATENCY 200
+#define DRAM_RQ_SIZE 16
+#define DRAM_STALLS_MODULO 16
+#define PIPELINE_FLUSH_LATENCY 300
+
+typedef struct {
+  int cycles_left;
+  int data_length;
+  unsigned base_addr;
+  unsigned *data;
+} dram_req_t;
+
+class Simulator {
+public:
+  
+  Simulator(RAM *ram);
+  virtual ~Simulator();
+
+  bool is_busy();  
+  void reset();
+  void step();
+  void flush_caches(uint32_t mem_addr, uint32_t size);  
+  bool run();
+  void print_stats(std::ostream& out);
+
+private:  
+
+#ifndef USE_MULTICORE
+  void ibus_driver();
+#endif
+
+  void dbus_driver();
+  void io_handler();  
+  void send_snoops(uint32_t mem_addr, uint32_t size);
+  void wait(uint32_t cycles);
+
+  uint64_t total_cycles_;
+  bool dram_stalled_;
+  bool I_dram_stalled_;
+  std::vector<dram_req_t> dram_req_vec_;
+  std::vector<dram_req_t> I_dram_req_vec_;
+  RAM *ram_;
+#ifdef USE_MULTICORE
+  VVortex_Socket *vortex_;
+#else
+  VVortex *vortex_;
+#endif
+#ifdef VCD_OUTPUT
+  VerilatedVcdC *trace_;
+#endif
+};

hw/simulate/testbench.cpp

@@ -0,0 +1,120 @@
+#include "simulator.h"
+#include <iostream>
+#include <fstream>
+#include <iomanip>
+
+#define NUM_TESTS 46
+
+int main(int argc, char **argv)
+{
+
+	// Verilated::debug(1);
+
+	Verilated::commandArgs(argc, argv);
+
+//#define ALL_TESTS
+#ifdef ALL_TESTS
+  bool passed = true;
+
+  std::string tests[NUM_TESTS] = {
+	 	"../../benchmarks/riscv_tests/rv32ui-p-add.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-and.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-auipc.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-beq.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-bge.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-blt.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lh.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lhu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lui.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-lw.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-or.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-ori.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sb.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sh.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-simple.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sll.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-slli.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-slt.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-slti.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sltu.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sra.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-srai.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-srl.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-srli.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sub.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-sw.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-xor.hex",
+	 	"../../benchmarks/riscv_tests/rv32ui-p-xori.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-div.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-divu.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-mul.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-mulh.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-mulhu.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-rem.hex",
+	 	"../../benchmarks/riscv_tests/rv32um-p-remu.hex"
+	 };
+
+	for (std::string s : tests) {
+		std::cerr << DEFAULT << "\n---------------------------------------\n";
+
+		std::cerr << s << std::endl;
+
+		RAM ram;
+		loadHexImpl(s.c_str(), &ram);
+
+		Simulator simulator(&ram);
+		bool curr = simulator.run();
+
+		if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
+		if (!curr) std::cerr << RED   << "Test Failed: " << s << std::endl;
+		std::cerr << DEFAULT;
+		passed = passed && curr;
+	}
+
+	std::cerr << DEFAULT << "\n***************************************\n";
+
+	if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
+	if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
+
+	return !passed;
+
+#else
+
+	char testing[] = "../../runtime/tests/simple/vx_simple_main.hex";
+	//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
+	//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
+
+	// const char *testing;
+
+	// if (argc >= 2) {
+	//     testing = argv[1];
+	// } else {
+	//     testing = "../../kernel/vortex_test.hex";
+	// }
+
+  std::cerr << testing << std::endl;
+
+  RAM ram;
+	loadHexImpl(testing, &ram);
+
+	Simulator simulator(&ram);
+	bool curr = simulator.run();
+
+	if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
+	if (!curr) std::cerr << RED   << "Test Failed: " << testing << std::endl;
+
+    return !curr;
+
+#endif
+}