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refactoring fixes

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This commit is contained in:
Blaise Tine
2020-04-14 19:39:59 -04:00
parent 22c8da7490
commit 12dc4d6874
624 changed files with 600 additions and 28528 deletions
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4
hw/Makefile
View File

@@ -1,12 +1,12 @@
all: RUNFILE
INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
INCLUDE = -I./rtl/ -I./rtl/shared_memory -I./rtl/cache -I./rtl/generic_cache -I./rtl/generic_cache/interfaces -I./rtl/interfaces/ -I./rtl/pipe_regs/ -I./rtl/compat/ -I./rtl/simulate
SINGLE_CORE = Vortex.v
MULTI_CORE = Vortex_Socket.v
EXE += --exe ./simulate/test_bench.cpp ./simulate/simulator.cpp
EXE += --exe ./simulate/testbench.cpp ./simulate/simulator.cpp
VF += -compiler gcc --language 1800-2009

6
hw/gen_config.py
View File

@@ -20,13 +20,13 @@ print('Custom params:', ', '.join(['='.join(x) for x in defines.items()]))
parser = argparse.ArgumentParser()
parser.add_argument('--outc', default='none', help='Output C header')
parser.add_argument('--outv', default='none', help='Output Verilog header')
parser.add_argument('--rtl_locations', action='store_true', help='use outc and outv for rtl and rtl/simulate')
parser.add_argument('--rtl_locations', action='store_true', help='use outc and outv for rtl and verilator')
args = parser.parse_args()
if args.rtl_locations:
args.outc = path.join(rtl_root, 'simulate/VX_define.h')
args.outv = path.join(rtl_root, 'VX_define_synth.v')
args.outv = path.join(rtl_root, 'rtl/VX_define_synth.v')
if args.outc == 'none' and args.outv == 'none':
print('Warning: not emitting any files. Specify arguments')
@@ -100,7 +100,7 @@ if args.outc != 'none':
// Translated from VX_define.v:
'''[1:].format(date=datetime.now()), file=f)
with open(path.join(rtl_root, 'VX_define.v'), 'r') as r:
with open(path.join(rtl_root, 'rtl/VX_define.v'), 'r') as r:
for line in r:
if in_expansion:
f.write(post_process_line(line))

152
hw/modelsim/Makefile
View File

@@ -6,83 +6,83 @@ ALL:sim
SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../VX_define.v \
../VX_define_synth.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_countones.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_generic_pe.v \
../cache/cache_set.v \
../cache/VX_cache_data_per_index.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \
../../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v
../rtl/VX_define.v \
../rtl/VX_define_synth.v \
../rtl/interfaces/VX_branch_response_inter.v \
../rtl/interfaces/VX_csr_req_inter.v \
../rtl/interfaces/VX_csr_wb_inter.v \
../rtl/interfaces/VX_dcache_request_inter.v \
../rtl/interfaces/VX_dcache_response_inter.v \
../rtl/interfaces/VX_dram_req_rsp_inter.v \
../rtl/interfaces/VX_exec_unit_req_inter.v \
../rtl/interfaces/VX_frE_to_bckE_req_inter.v \
../rtl/interfaces/VX_gpr_clone_inter.v \
../rtl/interfaces/VX_gpr_data_inter.v \
../rtl/interfaces/VX_gpr_jal_inter.v \
../rtl/interfaces/VX_gpr_read_inter.v \
../rtl/interfaces/VX_gpr_wspawn_inter.v \
../rtl/interfaces/VX_gpu_inst_req_inter.v \
../rtl/interfaces/VX_icache_request_inter.v \
../rtl/interfaces/VX_icache_response_inter.v \
../rtl/interfaces/VX_inst_exec_wb_inter.v \
../rtl/interfaces/VX_inst_mem_wb_inter.v \
../rtl/interfaces/VX_inst_meta_inter.v \
../rtl/interfaces/VX_jal_response_inter.v \
../rtl/interfaces/VX_join_inter.v \
../rtl/interfaces/VX_lsu_req_inter.v \
../rtl/interfaces/VX_mem_req_inter.v \
../rtl/interfaces/VX_mw_wb_inter.v \
../rtl/interfaces/VX_warp_ctl_inter.v \
../rtl/interfaces/VX_wb_inter.v \
../rtl/interfaces/VX_wstall_inter.v \
../rtl/VX_alu.v \
../rtl/VX_back_end.v \
../rtl/VX_csr_handler.v \
../rtl/VX_csr_wrapper.v \
../rtl/VX_decode.v \
../rtl/VX_dmem_controller.v \
../rtl/VX_execute_unit.v \
../rtl/VX_fetch.v \
../rtl/VX_front_end.v \
../rtl/VX_generic_priority_encoder.v \
../rtl/VX_generic_register.v \
../rtl/VX_generic_stack.v \
../rtl/VX_gpgpu_inst.v \
../rtl/VX_gpr.v \
../rtl/VX_gpr_stage.v \
../rtl/VX_gpr_wrapper.v \
../rtl/VX_inst_multiplex.v \
../rtl/VX_lsu.v \
../rtl/VX_lsu_addr_gen.v \
../rtl/VX_priority_encoder.v \
../rtl/VX_priority_encoder_w_mask.v \
../rtl/VX_scheduler.v \
../rtl/VX_warp.v \
../rtl/VX_countones.v \
../rtl/VX_warp_scheduler.v \
../rtl/VX_writeback.v \
../rtl/Vortex.v \
../rtl/byte_enabled_simple_dual_port_ram.v \
../rtl/cache/VX_Cache_Bank.v \
../rtl/cache/VX_cache_bank_valid.v \
../rtl/cache/VX_cache_data.v \
../rtl/cache/VX_d_cache.v \
../rtl/cache/VX_generic_pe.v \
../rtl/cache/cache_set.v \
../rtl/cache/VX_cache_data_per_index.v \
../rtl/pipe_regs/VX_d_e_reg.v \
../rtl/pipe_regs/VX_f_d_reg.v \
../rtl/shared_memory/VX_bank_valids.v \
../rtl/shared_memory/VX_priority_encoder_sm.v \
../rtl/shared_memory/VX_shared_memory.v \
../rtl/shared_memory/VX_shared_memory_block.v \
../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \
../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# ../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h

112
hw/modelsim/modelsim.mpf
View File

@@ -2112,117 +2112,117 @@ Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 56
Project_File_0 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory.v
Project_File_0 = ../rtl/shared_memory/VX_shared_memory.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 54 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_clone_inter.v
Project_File_1 = ../rtl/interfaces/VX_gpr_clone_inter.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 31 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = /nethome/felsabbagh3/research/Vortex/rtl/icarus/vortex_tb.v
Project_File_2 = ../rtl/icarus/vortex_tb.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = /nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v
Project_File_3 = ../rtl/VX_front_end.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v
Project_File_4 = ../rtl/interfaces/VX_lsu_req_inter.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 44 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v
Project_File_5 = ../rtl/interfaces/VX_branch_response_inter.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 23 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v
Project_File_6 = ../rtl/interfaces/VX_wstall_inter.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 49 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v
Project_File_7 = ../rtl/interfaces/VX_gpr_wspawn_inter.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v
Project_File_8 = ../rtl/VX_generic_priority_encoder.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1572058635 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = /nethome/felsabbagh3/research/Vortex/rtl/cache/cache_set.v
Project_File_9 = ../rtl/cache/cache_set.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v
Project_File_10 = ../rtl/interfaces/VX_inst_exec_wb_inter.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 39 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_cache_bank_valid.v
Project_File_11 = ../rtl/cache/VX_cache_bank_valid.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = /nethome/felsabbagh3/research/Vortex/rtl/VX_alu.v
Project_File_12 = ../rtl/VX_alu.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v
Project_File_13 = ../rtl/shared_memory/VX_bank_valids.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 51 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_join_inter.v
Project_File_14 = ../rtl/interfaces/VX_join_inter.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 43 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = /nethome/felsabbagh3/research/Vortex/rtl/VX_csr_handler.v
Project_File_15 = ../rtl/VX_csr_handler.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = /nethome/felsabbagh3/research/Vortex/rtl/VX_dmem_controller.v
Project_File_16 = ../rtl/VX_dmem_controller.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v
Project_File_17 = ../rtl/interfaces/VX_frE_to_bckE_req_inter.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_exec_unit_req_inter.v
Project_File_18 = ../rtl/interfaces/VX_exec_unit_req_inter.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_cache_data.v
Project_File_19 = ../rtl/cache/VX_cache_data.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_register.v
Project_File_20 = ../rtl/VX_generic_register.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v
Project_File_21 = ../rtl/interfaces/VX_jal_response_inter.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 42 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_22 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Bank.v
Project_File_22 = ../rtl/cache/VX_Cache_Bank.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v
Project_File_23 = ../rtl/interfaces/VX_csr_wb_inter.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_24 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v
Project_File_24 = ../rtl/interfaces/VX_gpu_inst_req_inter.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 36 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_25 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wb_inter.v
Project_File_25 = ../rtl/interfaces/VX_wb_inter.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 48 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_26 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v
Project_File_26 = ../rtl/interfaces/VX_icache_response_inter.v
Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 38 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_27 = /nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v
Project_File_27 = ../rtl/VX_csr_wrapper.v
Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572061058 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_28 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_read_inter.v
Project_File_28 = ../rtl/interfaces/VX_gpr_read_inter.v
Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 34 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_29 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mw_wb_inter.v
Project_File_29 = ../rtl/interfaces/VX_mw_wb_inter.v
Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 46 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_30 = /nethome/felsabbagh3/research/Vortex/rtl/byte_enabled_simple_dual_port_ram.v
Project_File_30 = ../rtl/byte_enabled_simple_dual_port_ram.v
Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_31 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v
Project_File_31 = ../rtl/interfaces/VX_dcache_request_inter.v
Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_32 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_data_inter.v
Project_File_32 = ../rtl/interfaces/VX_gpr_data_inter.v
Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 32 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_33 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_set_bit.v
Project_File_33 = ../rtl/shared_memory/VX_set_bit.v
Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 53 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_34 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v
Project_File_34 = ../rtl/interfaces/VX_dcache_response_inter.v
Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_35 = /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v
Project_File_35 = ../rtl/VX_define.v
Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1572058635 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_36 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v
Project_File_36 = ../rtl/interfaces/VX_csr_req_inter.v
Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_37 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v
Project_File_37 = ../rtl/interfaces/VX_inst_mem_wb_inter.v
Project_File_P_37 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 40 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_38 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v
Project_File_38 = ../rtl/interfaces/VX_icache_request_inter.v
Project_File_P_38 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 37 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_39 = /nethome/felsabbagh3/research/Vortex/rtl/VX_execute_unit.v
Project_File_39 = ../rtl/VX_execute_unit.v
Project_File_P_39 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_40 = /nethome/felsabbagh3/research/Vortex/rtl/cache/bank.v
Project_File_40 = ../rtl/cache/bank.v
Project_File_P_40 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_41 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v
Project_File_41 = ../rtl/interfaces/VX_mem_req_inter.v
Project_File_P_41 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 45 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_42 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dram_req_rsp_inter.v
Project_File_42 = ../rtl/interfaces/VX_dram_req_rsp_inter.v
Project_File_P_42 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1572058636 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_43 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_priority_encoder_sm.v
Project_File_43 = ../rtl/shared_memory/VX_priority_encoder_sm.v
Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 52 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_44 = /nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v
Project_File_44 = ../rtl/VX_back_end.v
Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_45 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_warp_ctl_inter.v
Project_File_45 = ../rtl/interfaces/VX_warp_ctl_inter.v
Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 47 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_46 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Block_DM.v
Project_File_46 = ../rtl/cache/VX_Cache_Block_DM.v
Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_47 = /nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v
Project_File_47 = ../rtl/VX_fetch.v
Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_48 = /nethome/felsabbagh3/research/Vortex/rtl/Vortex.v
Project_File_48 = ../rtl/Vortex.v
Project_File_P_48 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_49 = /nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v
Project_File_49 = ../rtl/VX_decode.v
Project_File_P_49 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_50 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache_encapsulate.v
Project_File_50 = ../rtl/cache/VX_d_cache_encapsulate.v
Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_51 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory_block.v
Project_File_51 = ../rtl/shared_memory/VX_shared_memory_block.v
Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 55 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_52 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v
Project_File_52 = ../rtl/interfaces/VX_inst_meta_inter.v
Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_53 = /nethome/felsabbagh3/research/Vortex/rtl/pipe_regs/VX_d_e_reg.v
Project_File_53 = ../rtl/pipe_regs/VX_d_e_reg.v
Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 50 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_54 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v
Project_File_54 = ../rtl/cache/VX_d_cache.v
Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1572058635 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_55 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_jal_inter.v
Project_File_55 = ../rtl/interfaces/VX_gpr_jal_inter.v
Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 33 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0

6
hw/modelsim/vortex_tb.v
View File

@@ -78,7 +78,7 @@ reg[31:0] io_data;
// Rsp
reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_i;
reg out_ebreak;
reg out_ebreak;
reg[31:0] hi;
@@ -87,9 +87,7 @@ reg out_ebreak;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/mains/simple/vx_simple_main.hex");
// load_file("../../emulator/riscv_tests/rv32ui-p-add.hex");
//load_file("../../kernel/vortex_test.hex");
load_file("../../runtime/tests/simple/vx_simple_main.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;

52
hw/old_rtl/Makefile
View File

@@ -1,52 +0,0 @@
all: RUNFILE
# /rf2_256x128_wm1/
BaseMEM=../models/memory/cln28hpm
INCLUDE=-I. -Ishared_memory -Icache -I$(BaseMEM)/rf2_128x128_wm1/ -I$(BaseMEM)/rf2_256x128_wm1/ -I$(BaseMEM)/rf2_256x19_wm0/ -I$(BaseMEM)/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ -Isimulate
FILE=Vortex.v
EXE=--exe ./simulate/test_bench.cpp
COMP=--compiler gcc
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT
# WNO=
# LIGHTW=
LIGHTW=-Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
CF=-CFLAGS '-std=c++11 -O3'
DEB=--trace --prof-cfuncs -DVL_DEBUG=1
MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
# -LDFLAGS '-lsystemc'
VERILATOR:
echo "#define VCD_OFF" > simulate/tb_debug.h
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
VERILATORnoWarnings:
echo "#define VCD_OFF" > simulate/tb_debug.h
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(WNO) $(DEB)
compdebug:
echo "#define VCD_OUTPUT" > simulate/tb_debug.h
verilator_bin_dbg $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '-std=c++11 -DVL_DEBUG' $(WNO) $(DEB)
RUNFILE: VERILATOR
$(MAKECPP)
debug: compdebug
$(MAKECPP)
w: VERILATORnoWarnings
$(MAKECPP)
clean:
rm -rf obj_dir

6
hw/opae/README
View File

@@ -7,7 +7,7 @@ source /export/fpga/bin/setup-fpga-env fpga-pac-a10
## Vortex Run commands ##
#########################
## Synthesis
cd ~/dev/Vortex/driver/hw/
cd /driver/hw/
# Configure a Quartus build area
afu_synth_setup -s sources.txt build_fpga
cd build_fpga
@@ -27,13 +27,13 @@ fpgaconf vortex_afu.gbs
# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
#fpgaconf --bus 0xaf vortex_afu.gbs
## Running the Test case
cd ../../sw/opae
cd /driver/opae
make clean
make
# For shared library
export LD_LIBRARY_PATH=${PWD}:$LD_LIBRARY_PATH
# Run the program
cd ../../tests/basic
cd /driver/tests/basic
make clean
make
./basic

220
hw/opae/sources.txt
View File

@@ -3,117 +3,117 @@ vortex_afu.json
+define+GLOBAL_BLOCK_SIZE_BYTES=64
+incdir+.
+incdir+../../rtl
+incdir+../../rtl/shared_memory
+incdir+../../rtl/cache
+incdir+../../rtl/VX_cache
+incdir+../../rtl/interfaces
+incdir+../../rtl/pipe_regs
+incdir+../../rtl/compat
+incdir+../rtl
+incdir+../rtl/shared_memory
+incdir+../rtl/cache
+incdir+../rtl/generic_cache
+incdir+../rtl/interfaces
+incdir+../rtl/pipe_regs
+incdir+../rtl/compat
../../rtl/VX_define_synth.v
../../rtl/VX_define.v
../../rtl/VX_cache/VX_cache_config.v
../../rtl/Vortex_Socket.v
../../rtl/Vortex_Cluster.v
../../rtl/Vortex.v
../../rtl/VX_front_end.v
../../rtl/VX_back_end.v
../../rtl/VX_fetch.v
../../rtl/VX_scheduler.v
../../rtl/VX_execute_unit.v
../../rtl/VX_warp.v
../../rtl/VX_icache_stage.v
../../rtl/VX_gpr_wrapper.v
../../rtl/byte_enabled_simple_dual_port_ram.v
../../rtl/VX_gpgpu_inst.v
../../rtl/VX_writeback.v
../../rtl/VX_countones.v
../../rtl/VX_csr_handler.v
../../rtl/VX_csr_pipe.v
../../rtl/VX_generic_queue_ll.v
../../rtl/VX_warp_scheduler.v
../../rtl/VX_priority_encoder.v
../../rtl/VX_generic_queue.v
../../rtl/pipe_regs/VX_f_d_reg.v
../../rtl/pipe_regs/VX_i_d_reg.v
../../rtl/pipe_regs/VX_d_e_reg.v
../../rtl/VX_gpr.v
../../rtl/VX_gpr_stage.v
../../rtl/VX_dmem_controller.v
../../rtl/VX_alu.v
../../rtl/VX_generic_stack.v
../../rtl/VX_generic_priority_encoder.v
../../rtl/VX_csr_data.v
../../rtl/VX_lsu.v
../../rtl/VX_decode.v
../../rtl/VX_inst_multiplex.v
../../rtl/VX_csr_wrapper.v
../../rtl/VX_priority_encoder_w_mask.v
../../rtl/VX_generic_register.v
../../rtl/VX_lsu_addr_gen.v
../../rtl/compat/VX_mult.v
../../rtl/compat/VX_divide.v
../../rtl/VX_cache/VX_snp_fwd_arb.v
../../rtl/VX_cache/VX_cache_dram_req_arb.v
../../rtl/VX_cache/VX_cache_dfq_queue.v
../../rtl/VX_cache/VX_cache_wb_sel_merge.v
../../rtl/VX_cache/VX_mrv_queue.v
../../rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v
../../rtl/VX_cache/VX_tag_data_access.v
../../rtl/VX_cache/VX_cache.v
../../rtl/VX_cache/VX_cache_core_req_bank_sel.v
../../rtl/VX_cache/VX_cache_req_queue.v
../../rtl/VX_cache/VX_bank.v
../../rtl/VX_cache/VX_cache_miss_resrv.v
../../rtl/VX_cache/VX_fill_invalidator.v
../../rtl/VX_cache/VX_tag_data_structure.v
../../rtl/VX_cache/VX_prefetcher.v
../../rtl/cache/VX_generic_pe.v
../../rtl/cache/cache_set.v
../../rtl/cache/VX_d_cache.v
../../rtl/cache/VX_Cache_Bank.v
../../rtl/cache/VX_cache_data_per_index.v
../../rtl/cache/VX_d_cache_encapsulate.v
../../rtl/cache/VX_cache_bank_valid.v
../../rtl/cache/VX_cache_data.v
../../rtl/shared_memory/VX_shared_memory_block.v
../../rtl/shared_memory/VX_priority_encoder_sm.v
../../rtl/shared_memory/VX_shared_memory.v
../../rtl/shared_memory/VX_bank_valids.v
../../rtl/interfaces/VX_exec_unit_req_inter.v
../../rtl/interfaces/VX_branch_response_inter.v
../../rtl/interfaces/VX_inst_meta_inter.v
../../rtl/interfaces/VX_join_inter.v
../../rtl/interfaces/VX_icache_response_inter.v
../../rtl/interfaces/VX_gpr_wspawn_inter.v
../../rtl/interfaces/VX_inst_exec_wb_inter.v
../../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
../../rtl/interfaces/VX_csr_req_inter.v
../../rtl/interfaces/VX_icache_request_inter.v
../../rtl/interfaces/VX_gpu_dcache_res_inter.v
../../rtl/interfaces/VX_frE_to_bckE_req_inter.v
../../rtl/interfaces/VX_dram_req_rsp_inter.v
../../rtl/interfaces/VX_dcache_request_inter.v
../../rtl/interfaces/VX_gpr_data_inter.v
../../rtl/interfaces/VX_dcache_response_inter.v
../../rtl/interfaces/VX_csr_wb_inter.v
../../rtl/interfaces/VX_gpu_dcache_req_inter.v
../../rtl/interfaces/VX_lsu_req_inter.v
../../rtl/interfaces/VX_gpu_snp_req_rsp.v
../../rtl/interfaces/VX_mw_wb_inter.v
../../rtl/interfaces/VX_gpr_jal_inter.v
../../rtl/interfaces/VX_gpu_inst_req_inter.v
../../rtl/interfaces/VX_wstall_inter.v
../../rtl/interfaces/VX_wb_inter.v
../../rtl/interfaces/VX_gpr_clone_inter.v
../../rtl/interfaces/VX_gpr_read_inter.v
../../rtl/interfaces/VX_mem_req_inter.v
../../rtl/interfaces/VX_jal_response_inter.v
../../rtl/interfaces/VX_warp_ctl_inter.v
../../rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
../../rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
../../rtl/interfaces/VX_inst_mem_wb_inter.v
../rtl/VX_define_synth.v
../rtl/VX_define.v
../rtl/generic_cache/VX_cache_config.v
../rtl/Vortex_Socket.v
../rtl/Vortex_Cluster.v
../rtl/Vortex.v
../rtl/VX_front_end.v
../rtl/VX_back_end.v
../rtl/VX_fetch.v
../rtl/VX_scheduler.v
../rtl/VX_execute_unit.v
../rtl/VX_warp.v
../rtl/VX_icache_stage.v
../rtl/VX_gpr_wrapper.v
../rtl/byte_enabled_simple_dual_port_ram.v
../rtl/VX_gpgpu_inst.v
../rtl/VX_writeback.v
../rtl/VX_countones.v
../rtl/VX_csr_handler.v
../rtl/VX_csr_pipe.v
../rtl/VX_generic_queue_ll.v
../rtl/VX_warp_scheduler.v
../rtl/VX_priority_encoder.v
../rtl/VX_generic_queue.v
../rtl/pipe_regs/VX_f_d_reg.v
../rtl/pipe_regs/VX_i_d_reg.v
../rtl/pipe_regs/VX_d_e_reg.v
../rtl/VX_gpr.v
../rtl/VX_gpr_stage.v
../rtl/VX_dmem_controller.v
../rtl/VX_alu.v
../rtl/VX_generic_stack.v
../rtl/VX_generic_priority_encoder.v
../rtl/VX_csr_data.v
../rtl/VX_lsu.v
../rtl/VX_decode.v
../rtl/VX_inst_multiplex.v
../rtl/VX_csr_wrapper.v
../rtl/VX_priority_encoder_w_mask.v
../rtl/VX_generic_register.v
../rtl/VX_lsu_addr_gen.v
../rtl/compat/VX_mult.v
../rtl/compat/VX_divide.v
../rtl/generic_cache/VX_snp_fwd_arb.v
../rtl/generic_cache/VX_cache_dram_req_arb.v
../rtl/generic_cache/VX_cache_dfq_queue.v
../rtl/generic_cache/VX_cache_wb_sel_merge.v
../rtl/generic_cache/VX_mrv_queue.v
../rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v
../rtl/generic_cache/VX_tag_data_access.v
../rtl/generic_cache/generic_cache.v
../rtl/generic_cache/VX_cache_core_req_bank_sel.v
../rtl/generic_cache/VX_cache_req_queue.v
../rtl/generic_cache/VX_bank.v
../rtl/generic_cache/VX_cache_miss_resrv.v
../rtl/generic_cache/VX_fill_invalidator.v
../rtl/generic_cache/VX_tag_data_structure.v
../rtl/generic_cache/VX_prefetcher.v
../rtl/cache/VX_generic_pe.v
../rtl/cache/cache_set.v
../rtl/cache/VX_d_cache.v
../rtl/cache/VX_Cache_Bank.v
../rtl/cache/VX_cache_data_per_index.v
../rtl/cache/VX_d_cache_encapsulate.v
../rtl/cache/VX_cache_bank_valid.v
../rtl/cache/VX_cache_data.v
../rtl/shared_memory/VX_shared_memory_block.v
../rtl/shared_memory/VX_priority_encoder_sm.v
../rtl/shared_memory/VX_shared_memory.v
../rtl/shared_memory/VX_bank_valids.v
../rtl/interfaces/VX_exec_unit_req_inter.v
../rtl/interfaces/VX_branch_response_inter.v
../rtl/interfaces/VX_inst_meta_inter.v
../rtl/interfaces/VX_join_inter.v
../rtl/interfaces/VX_icache_response_inter.v
../rtl/interfaces/VX_gpr_wspawn_inter.v
../rtl/interfaces/VX_inst_exec_wb_inter.v
../rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
../rtl/interfaces/VX_csr_req_inter.v
../rtl/interfaces/VX_icache_request_inter.v
../rtl/interfaces/VX_gpu_dcache_res_inter.v
../rtl/interfaces/VX_frE_to_bckE_req_inter.v
../rtl/interfaces/VX_dram_req_rsp_inter.v
../rtl/interfaces/VX_dcache_request_inter.v
../rtl/interfaces/VX_gpr_data_inter.v
../rtl/interfaces/VX_dcache_response_inter.v
../rtl/interfaces/VX_csr_wb_inter.v
../rtl/interfaces/VX_gpu_dcache_req_inter.v
../rtl/interfaces/VX_lsu_req_inter.v
../rtl/interfaces/VX_gpu_snp_req_rsp.v
../rtl/interfaces/VX_mw_wb_inter.v
../rtl/interfaces/VX_gpr_jal_inter.v
../rtl/interfaces/VX_gpu_inst_req_inter.v
../rtl/interfaces/VX_wstall_inter.v
../rtl/interfaces/VX_wb_inter.v
../rtl/interfaces/VX_gpr_clone_inter.v
../rtl/interfaces/VX_gpr_read_inter.v
../rtl/interfaces/VX_mem_req_inter.v
../rtl/interfaces/VX_jal_response_inter.v
../rtl/interfaces/VX_warp_ctl_inter.v
../rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
../rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
../rtl/interfaces/VX_inst_mem_wb_inter.v
ccip_interface_reg.sv
ccip_std_afu.sv

2
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
View File

@@ -1,6 +1,6 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_DRAM_DCACHE_REQ

2
hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
View File

@@ -1,7 +1,7 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_DRAM_DCACHE_RES

2
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v
View File

@@ -1,6 +1,6 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_DCACHE_REQ

2
hw/rtl/interfaces/VX_gpu_dcache_res_inter.v
View File

@@ -1,6 +1,6 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_DCACHE_RES

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
View File

@@ -1,7 +1,7 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_SNP_REQ

2
hw/rtl/interfaces/VX_gpu_snp_req_rsp.v
View File

@@ -1,4 +1,4 @@
`include "../VX_cache/VX_cache_config.v"
`include "../generic_cache/VX_cache_config.v"
`ifndef VX_GPU_SNP_REQ_RSP

0
hw/verilator/ram.h → hw/simulate/ram.h
View File

0
hw/verilator/simulator.cpp → hw/simulate/simulator.cpp
View File

0
hw/verilator/simulator.h → hw/simulate/simulator.h
View File

120
hw/simulate/testbench.cpp Normal file
View File

@@ -0,0 +1,120 @@
#include "simulator.h"
#include <iostream>
#include <fstream>
#include <iomanip>
#define NUM_TESTS 46
int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);
//#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
"../../benchmarks/riscv_tests/rv32ui-p-and.hex",
"../../benchmarks/riscv_tests/rv32ui-p-andi.hex",
"../../benchmarks/riscv_tests/rv32ui-p-auipc.hex",
"../../benchmarks/riscv_tests/rv32ui-p-beq.hex",
"../../benchmarks/riscv_tests/rv32ui-p-bge.hex",
"../../benchmarks/riscv_tests/rv32ui-p-bgeu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-blt.hex",
"../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
"../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
"../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lh.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lhu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lui.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lw.hex",
"../../benchmarks/riscv_tests/rv32ui-p-or.hex",
"../../benchmarks/riscv_tests/rv32ui-p-ori.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sb.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sh.hex",
"../../benchmarks/riscv_tests/rv32ui-p-simple.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sll.hex",
"../../benchmarks/riscv_tests/rv32ui-p-slli.hex",
"../../benchmarks/riscv_tests/rv32ui-p-slt.hex",
"../../benchmarks/riscv_tests/rv32ui-p-slti.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sltiu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sltu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sra.hex",
"../../benchmarks/riscv_tests/rv32ui-p-srai.hex",
"../../benchmarks/riscv_tests/rv32ui-p-srl.hex",
"../../benchmarks/riscv_tests/rv32ui-p-srli.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sub.hex",
"../../benchmarks/riscv_tests/rv32ui-p-sw.hex",
"../../benchmarks/riscv_tests/rv32ui-p-xor.hex",
"../../benchmarks/riscv_tests/rv32ui-p-xori.hex",
"../../benchmarks/riscv_tests/rv32um-p-div.hex",
"../../benchmarks/riscv_tests/rv32um-p-divu.hex",
"../../benchmarks/riscv_tests/rv32um-p-mul.hex",
"../../benchmarks/riscv_tests/rv32um-p-mulh.hex",
"../../benchmarks/riscv_tests/rv32um-p-mulhsu.hex",
"../../benchmarks/riscv_tests/rv32um-p-mulhu.hex",
"../../benchmarks/riscv_tests/rv32um-p-rem.hex",
"../../benchmarks/riscv_tests/rv32um-p-remu.hex"
};
for (std::string s : tests) {
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
RAM ram;
loadHexImpl(s.c_str(), &ram);
Simulator simulator(&ram);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
}
std::cerr << DEFAULT << "\n***************************************\n";
if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
char testing[] = "../../runtime/tests/simple/vx_simple_main.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-lw.hex";
//char testing[] = "../../benchmarks/riscv_tests/rv32ui-p-sw.hex";
// const char *testing;
// if (argc >= 2) {
// testing = argv[1];
// } else {
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Simulator simulator(&ram);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return !curr;
#endif
}

2
hw/syn/quartus/cache/Makefile vendored
View File

@@ -1,6 +1,6 @@
PROJECT = VX_d_cache
TOP_LEVEL_ENTITY = VX_d_cache
SRC_FILE = ../VX_d_cache.v
SRC_FILE = ../../../rtl/cache/VX_d_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family

4
hw/syn/quartus/top/Makefile
View File

@@ -1,6 +1,6 @@
PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex_Socket
SRC_FILE = ../Vortex.v
SRC_FILE = ../../../rtl/Vortex.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
@@ -57,7 +57,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization
$(PROJECT_FILES):
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat"
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../generic_cache;../shared_memory;../compat"
syn.chg:
$(STAMP) syn.chg

2
hw/syn/quartus/vx_cache/Makefile
View File

@@ -1,6 +1,6 @@
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../VX_cache.v
SRC_FILE = ../../../rtl/generic_cache/VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0

BIN
hw/syn/synopsys/Vortex.ddc
View File

Binary file not shown.

4
hw/syn/synopsys/esyn.tcl
View File

@@ -1,5 +1,5 @@
#set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
#set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set link_library [concat ./NanGate_15nm_OCL.db]
set symbol_library {}
set target_library [concat ./NanGate_15nm_OCL.db]

2
hw/syn/synopsys/fsyn.tcl
View File

@@ -1,4 +1,4 @@
set search_path [concat ../models/memory/cln28hpm/rf2_128x128_wm1 ../models/memory/cln28hpm/rf2_256x128_wm1 ../models/memory/cln28hpm/rf2_256_19_wm0 ../models/memory/cln28hpm/rf2_32x128_wm1 ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache]
set search_path [concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../models/memory/cln28hpm/rf2_256x128_wm1 ../../models/memory/cln28hpm/rf2_256_19_wm0 ../../models/memory/cln28hpm/rf2_32x128_wm1 ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache]
set link_library [concat NanGate_15nm_OCL.db]
set symbol_library {}
set target_library [concat NanGate_15nm_OCL.db]

2
hw/syn/synopsys/syn.tcl
View File

@@ -1,4 +1,4 @@
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../../rtl/ ../../rtl/interfaces ../../rtl/pipe_regs ../../rtl/shared_memory ../../rtl/cache ../../models/memory/cln28hpm/2d_hardmacro_db]
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
set symbol_library {}
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]

2
hw/unit_tests/generic_queue/Makefile
View File

@@ -1,7 +1,7 @@
all: testbench.iv
testbench.iv: testbench.v
iverilog testbench.v -o testbench.iv -I ../..
iverilog testbench.v -o testbench.iv -I ../../rtl/
run: testbench.iv
! vvp testbench.iv | grep 'ERROR' || false

120
hw/verilator/testbench.cpp
View File

@@ -1,120 +0,0 @@
#include "simulator.h"
#include <iostream>
#include <fstream>
#include <iomanip>
#define NUM_TESTS 46
int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);
//#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../emulator/riscv_tests/rv32ui-p-add.hex",
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
"../../emulator/riscv_tests/rv32ui-p-and.hex",
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
"../../emulator/riscv_tests/rv32ui-p-or.hex",
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
"../../emulator/riscv_tests/rv32um-p-div.hex",
"../../emulator/riscv_tests/rv32um-p-divu.hex",
"../../emulator/riscv_tests/rv32um-p-mul.hex",
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
"../../emulator/riscv_tests/rv32um-p-rem.hex",
"../../emulator/riscv_tests/rv32um-p-remu.hex"
};
for (std::string s : tests) {
std::cerr << DEFAULT << "\n---------------------------------------\n";
std::cerr << s << std::endl;
RAM ram;
loadHexImpl(s.c_str(), &ram);
Simulator simulator(&ram);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
std::cerr << DEFAULT;
passed = passed && curr;
}
std::cerr << DEFAULT << "\n***************************************\n";
if (passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
//char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
//char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
// const char *testing;
// if (argc >= 2) {
// testing = argv[1];
// } else {
// testing = "../../kernel/vortex_test.hex";
// }
std::cerr << testing << std::endl;
RAM ram;
loadHexImpl(testing, &ram);
Simulator simulator(&ram);
bool curr = simulator.run();
if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return !curr;
#endif
}