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texture unit dcache arbitration

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This commit is contained in:
Blaise Tine
2021-03-18 14:23:53 -04:00
parent 6febdf7399
commit 124acfbf12
14 changed files with 606 additions and 115 deletions
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16
hw/rtl/interfaces/VX_dcache_core_req_if.v
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@@ -4,18 +4,18 @@
`include "../cache/VX_cache_config.vh"
interface VX_dcache_core_req_if #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0] rw;
wire [NUM_REQS-1:0][WORD_SIZE-1:0] byteen;
wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] tag;
wire [NUM_REQS-1:0] ready;
wire [LANES-1:0] valid;
wire [LANES-1:0] rw;
wire [LANES-1:0][WORD_SIZE-1:0] byteen;
wire [LANES-1:0][`WORD_ADDR_WIDTH-1:0] addr;
wire [LANES-1:0][`WORD_WIDTH-1:0] data;
wire [LANES-1:0][CORE_TAG_WIDTH-1:0] tag;
wire [LANES-1:0] ready;
endinterface

10
hw/rtl/interfaces/VX_dcache_core_rsp_if.v
View File

@@ -4,15 +4,15 @@
`include "../cache/VX_cache_config.vh"
interface VX_dcache_core_rsp_if #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire ready;
wire [LANES-1:0] valid;
wire [LANES-1:0][`WORD_WIDTH-1:0]data;
wire [CORE_TAG_WIDTH-1:0] tag;
wire ready;
endinterface