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Modelsim basic sim

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This commit is contained in:
felsabbagh3
2019-10-26 00:34:57 -04:00
parent 9110e8367e
commit 1181af1df2
25 changed files with 72 additions and 501 deletions
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14
rtl/cache/VX_cache_data.v vendored
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@@ -4,10 +4,11 @@
module VX_cache_data
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)
(
input wire clk, // Clock
@@ -31,7 +32,7 @@ module VX_cache_data
localparam NUMBER_BANKS = CACHE_BANKS;
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
wire currently_writing = (|we);
@@ -56,12 +57,11 @@ module VX_cache_data
assign dirty_use = dirty[addr];
genvar f;
genvar z;
always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end
integer f;
always @(posedge clk) begin : data_update
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];