Modelsim basic sim

2019-10-26 00:34:57 -04:00
parent 9110e8367e
commit 1181af1df2
25 changed files with 72 additions and 501 deletions
--- a/rtl/VX_lsu_addr_gen.v
+++ b/rtl/VX_lsu_addr_gen.v
@@ -1,3 +1,5 @@
+`include "VX_define.v"
+
 module VX_lsu_addr_gen (
 	input  wire[`NT_M1:0][31:0] base_address,
 	input  wire[31:0]           offset,