wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

adding CSR support to rtlsim driver

Browse Source
This commit is contained in:
Blaise Tine
2020-09-04 06:51:31 -04:00
parent dccea80b68
commit 112d8ab815
10 changed files with 167 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

71
hw/simulate/simulator.cpp
View File

@@ -22,6 +22,7 @@ Simulator::Simulator() {
dram_rsp_active_ = false;
snp_req_active_ = false;
csr_req_active_ = false;
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
@@ -163,15 +164,6 @@ void Simulator::eval_io_bus() {
vortex_->io_rsp_valid = 0;
}
void Simulator::eval_csr_bus() {
vortex_->csr_io_req_valid = 0;
vortex_->csr_io_req_coreid = 0;
vortex_->csr_io_req_addr = 0;
vortex_->csr_io_req_rw = 0;
vortex_->csr_io_req_data = 0;
vortex_->csr_io_rsp_ready = 1;
}
void Simulator::eval_snp_bus() {
if (snp_req_active_) {
if (vortex_->snp_rsp_valid) {
@@ -204,6 +196,27 @@ void Simulator::eval_snp_bus() {
}
}
void Simulator::eval_csr_bus() {
if (csr_req_active_) {
if (vortex_->csr_io_req_rw) {
if (vortex_->csr_io_req_ready) {
vortex_->snp_req_valid = 0;
csr_req_active_ = false;
}
} else {
if (vortex_->csr_io_rsp_valid) {
*csr_rsp_value_ = vortex_->csr_io_rsp_data;
vortex_->snp_req_valid = 0;
vortex_->csr_io_rsp_ready = 0;
csr_req_active_ = false;
}
}
} else {
vortex_->csr_io_req_valid = 0;
vortex_->csr_io_rsp_ready = 0;
}
}
void Simulator::wait(uint32_t cycles) {
for (int i = 0; i < cycles; ++i) {
this->step();
@@ -211,7 +224,9 @@ void Simulator::wait(uint32_t cycles) {
}
bool Simulator::is_busy() const {
return vortex_->busy || snp_req_active_;
return vortex_->busy
|| snp_req_active_
|| csr_req_active_;
}
void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
@@ -221,22 +236,52 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
if (0 == size)
return;
snp_req_active_ = true;
snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
vortex_->snp_req_addr = mem_addr / GLOBAL_BLOCK_SIZE;
vortex_->snp_req_tag = 0;
vortex_->snp_req_valid = 1;
vortex_->snp_rsp_ready = 1;
snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
--snp_req_size_;
pending_snp_reqs_ = 1;
snp_req_active_ = true;
#ifdef DBG_PRINT_CACHE_SNP
std::cout << timestamp << ": [sim] snp req: addr=" << std::hex << vortex_->snp_req_addr << std::dec << " tag=" << vortex_->snp_req_tag << " remain=" << snp_req_size_ << std::endl;
#endif
}
void Simulator::set_csr(int core_id, int addr, unsigned value) {
#ifndef NDEBUG
std::cout << timestamp << ": [sim] set_csr()" << std::endl;
#endif
vortex_->csr_io_req_valid = 1;
vortex_->csr_io_req_coreid = core_id;
vortex_->csr_io_req_addr = addr;
vortex_->csr_io_req_rw = 1;
vortex_->csr_io_req_data = value;
vortex_->csr_io_rsp_ready = 0;
csr_req_active_ = true;
}
void Simulator::get_csr(int core_id, int addr, unsigned *value) {
#ifndef NDEBUG
std::cout << timestamp << ": [sim] get_csr()" << std::endl;
#endif
vortex_->csr_io_req_valid = 1;
vortex_->csr_io_req_coreid = core_id;
vortex_->csr_io_req_addr = addr;
vortex_->csr_io_req_rw = 0;
vortex_->csr_io_rsp_ready = 1;
csr_rsp_value_ = value;
csr_req_active_ = true;
}
void Simulator::run() {
#ifndef NDEBUG
std::cout << timestamp << ": [sim] run()" << std::endl;

11
hw/simulate/simulator.h
View File

@@ -31,6 +31,8 @@ public:
Simulator();
virtual ~Simulator();
void attach_ram(RAM* ram);
void load_bin(const char* program_file);
void load_ihex(const char* program_file);
@@ -39,12 +41,14 @@ public:
void reset();
void step();
void wait(uint32_t cycles);
void flush_caches(uint32_t mem_addr, uint32_t size);
void attach_ram(RAM* ram);
void set_csr(int core_id, int addr, unsigned value);
void get_csr(int core_id, int addr, unsigned *value);
void run();
int get_last_wb_value(int reg) const;
void print_stats(std::ostream& out);
private:
@@ -60,8 +64,11 @@ private:
int dram_rsp_active_;
bool snp_req_active_;
bool csr_req_active_;
uint32_t snp_req_size_;
uint32_t pending_snp_reqs_;
uint32_t* csr_rsp_value_;
RAM *ram_;
VVortex *vortex_;