diff --git a/rtl/Vortex.qsf b/rtl/Vortex.qsf
index 638a44b5..ffec91eb 100644
--- a/rtl/Vortex.qsf
+++ b/rtl/Vortex.qsf
@@ -3,26 +3,26 @@ set_global_assignment -name TOP_LEVEL_ENTITY Vortex
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:29  MAY 12, 2019"
 set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/Vortex.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_alu.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context_slave.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_csr_handler.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_d_e_reg.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_decode.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_define.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_e_m_reg.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_execute.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_f_d_reg.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_fetch.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_forwarding.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_m_w_reg.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_memory.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_master_slave.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_slave.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_warp.v
-set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_writeback.v
+set_global_assignment -name VERILOG_FILE ./Vortex.v
+set_global_assignment -name VERILOG_FILE ./VX_alu.v
+set_global_assignment -name VERILOG_FILE ./VX_context.v
+set_global_assignment -name VERILOG_FILE ./VX_context_slave.v
+set_global_assignment -name VERILOG_FILE ./VX_csr_handler.v
+set_global_assignment -name VERILOG_FILE ./VX_d_e_reg.v
+set_global_assignment -name VERILOG_FILE ./VX_decode.v
+set_global_assignment -name VERILOG_FILE ./VX_define.v
+set_global_assignment -name VERILOG_FILE ./VX_e_m_reg.v
+set_global_assignment -name VERILOG_FILE ./VX_execute.v
+set_global_assignment -name VERILOG_FILE ./VX_f_d_reg.v
+set_global_assignment -name VERILOG_FILE ./VX_fetch.v
+set_global_assignment -name VERILOG_FILE ./VX_forwarding.v
+set_global_assignment -name VERILOG_FILE ./VX_m_w_reg.v
+set_global_assignment -name VERILOG_FILE ./VX_memory.v
+set_global_assignment -name VERILOG_FILE ./VX_register_file.v
+set_global_assignment -name VERILOG_FILE ./VX_register_file_master_slave.v
+set_global_assignment -name VERILOG_FILE ./VX_register_file_slave.v
+set_global_assignment -name VERILOG_FILE ./VX_warp.v
+set_global_assignment -name VERILOG_FILE ./VX_writeback.v
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name DEVICE 10AX115U3F45I2SG
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4