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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

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This commit is contained in:
Blaise Tine
2020-11-08 01:31:46 -08:00
parent b14007f930
commit 10505caae1
19 changed files with 602 additions and 534 deletions
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60
hw/rtl/cache/VX_snp_rsp_arb.v vendored
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@@ -16,37 +16,43 @@ module VX_snp_rsp_arb #(
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready
);
if (NUM_BANKS > 1) begin
wire sel_valid;
wire [`BANK_BITS-1:0] sel_idx;
wire [NUM_BANKS-1:0] sel_1hot;
wire sel_valid;
wire [`BANK_BITS-1:0] sel_idx;
wire [NUM_BANKS-1:0] sel_1hot;
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (per_bank_snp_rsp_valid),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (per_bank_snp_rsp_valid),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
wire stall = ~snp_rsp_ready && snp_rsp_valid;
wire stall = ~snp_rsp_ready && snp_rsp_valid;
VX_generic_register #(
.N(1 + SNP_REQ_TAG_WIDTH),
.PASSTHRU(NUM_BANKS <= 2)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({sel_valid, per_bank_snp_rsp_tag[sel_idx]}),
.out ({snp_rsp_valid, snp_rsp_tag})
);
VX_generic_register #(
.N(1 + SNP_REQ_TAG_WIDTH)
) core_wb_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({sel_valid, per_bank_snp_rsp_tag[sel_idx]}),
.out ({snp_rsp_valid, snp_rsp_tag})
);
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_snp_rsp_ready[i] = sel_1hot[i] && !stall;
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_snp_rsp_ready[i] = sel_1hot[i] && !stall;
end
end else begin
assign snp_rsp_valid = per_bank_snp_rsp_valid;
assign snp_rsp_tag = per_bank_snp_rsp_tag;
assign per_bank_snp_rsp_ready = snp_rsp_ready;
end
endmodule