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mrvq update ready + init ready as 1 in same cycle causing incorrect ready state

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This commit is contained in:
felsabbagh3
2020-05-16 18:52:30 -07:00
parent 794664363c
commit 101de6b138
3 changed files with 53 additions and 31 deletions
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7
hw/rtl/cache/VX_bank.v vendored
View File

@@ -105,6 +105,7 @@ module VX_bank #(
); );
`DEBUG_BEGIN `DEBUG_BEGIN
wire[31:0] debug_use_pc_st0; wire[31:0] debug_use_pc_st0;
wire[1:0] debug_wb_st0; wire[1:0] debug_wb_st0;
wire[4:0] debug_rd_st0; wire[4:0] debug_rd_st0;
@@ -340,7 +341,9 @@ module VX_bank #(
assign qual_from_mrvq_st0 = mrvq_pop; assign qual_from_mrvq_st0 = mrvq_pop;
`DEBUG_BEGIN `DEBUG_BEGIN
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0; assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0;
end
`DEBUG_END `DEBUG_END
VX_generic_register #( VX_generic_register #(
@@ -436,7 +439,9 @@ module VX_bank #(
); );
`DEBUG_BEGIN `DEBUG_BEGIN
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
end
`DEBUG_END `DEBUG_END
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
@@ -467,7 +472,9 @@ module VX_bank #(
); );
`DEBUG_BEGIN `DEBUG_BEGIN
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2; assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2;
end
`DEBUG_END `DEBUG_END
// Enqueue to miss reserv if it's a valid miss // Enqueue to miss reserv if it's a valid miss

5
hw/rtl/cache/VX_cache.v vendored
View File

@@ -128,6 +128,9 @@ module VX_cache #(
); );
`DEBUG_BEGIN `DEBUG_BEGIN
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
wire[31:0] debug_core_req_use_pc; wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb; wire[1:0] debug_core_req_wb;
wire[4:0] debug_core_req_rd; wire[4:0] debug_core_req_rd;
@@ -135,6 +138,8 @@ module VX_cache #(
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0]; assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
end
`DEBUG_END `DEBUG_END
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;

12
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -66,7 +66,14 @@ module VX_cache_miss_resrv #(
wire enqueue_possible = !miss_resrv_full; wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state;
`IGNORE_WARNINGS_BEGIN
wire [31:0] make_ready_push_full;
`IGNORE_WARNINGS_END
reg [MRVQ_SIZE-1:0] make_ready; reg [MRVQ_SIZE-1:0] make_ready;
reg [MRVQ_SIZE-1:0] make_ready_push;
reg [MRVQ_SIZE-1:0] valid_address_match; reg [MRVQ_SIZE-1:0] valid_address_match;
genvar i; genvar i;
@@ -91,6 +98,9 @@ module VX_cache_miss_resrv #(
wire update_ready = (|make_ready); wire update_ready = (|make_ready);
assign make_ready_push_full = ({31'b0, qual_mrvq_init} << enqueue_index);
assign make_ready_push = make_ready_push_full[MRVQ_SIZE-1:0];
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
valid_table <= 0; valid_table <= 0;
@@ -109,7 +119,7 @@ module VX_cache_miss_resrv #(
// update entry as 'ready' during DRAM fill response // update entry as 'ready' during DRAM fill response
if (update_ready) begin if (update_ready) begin
ready_table <= ready_table | make_ready; ready_table <= ready_table | make_ready | make_ready_push;
end end
if (mrvq_pop) begin if (mrvq_pop) begin