read and write complete

hw/unit_tests/cache/Makefile

@@ -1,4 +1,4 @@
-PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4
+PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4
  
 
 
@@ -16,7 +16,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
 INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs
 
 
-SRCS = cache_sim.cpp
+SRCS = cachesim.cpp testbench.cpp
 
 all: build
 

hw/unit_tests/cache/cache_sim.cpp

@@ -1,75 +0,0 @@
-#include "VVX_cache.h"
-#include "VVX_cache__Syms.h"
-#include "verilated.h"
-
-#include <verilated_vcd_c.h>
-
-#include <iostream>
-#include <vector>
-
-uint64_t timestamp = 0;
-
-double sc_time_stamp() { 
-  return timestamp;
-}
-
-void tick(VVX_cache* tb){
-	tb->eval();
-	tb->clk = 1; 
-
-	tb->eval();
-	tb->clk = 0;
-	tb->eval();
-}
-
-int main(int argc, char **argv){
-	Verilated::commandArgs(argc, argv); //passes the command args to the object
-
-	VVX_cache *tb = new VVX_cachee;
-	
-	//reset the cache
-	tb->reset = 1; 
-	tb->eval(); 
-	tb->reset = 0; 
-
-	//declare variables for output - data members in cache class
-	unsigned int clk;
-	bool full;
-	bool empty;
-	int size; 
-	int data_out; 
-
-	//assign inputs
-	tb->core_req_valid = 1;
-	tb->core_req_rw = 1; 
-
-	char byte_en[] = {}; //word size 4 bytes
-	tb->core_req_byteen[0] = 1;
-	tb->core_req_byteen[1] = 1;
-	tb->core_req_byteen[2] = 1;
-	tb->core_req_byteen[3] = 1;
-
-	char addr[4] = {0x1a, 0x2b, 0x3c, 0x4d}; //word addr width
-
-	tb->core_req_addr[0] = arr[0];
-	tb->core_req_addr[0] = arr[1];
-	tb->core_req_addr[0] = arr[2];
-	tb->core_req_addr[0] = arr[3];
-
-	//char req_data[] = {}; //word width
-	//tb->core_req_data
-
-	//char req_tag[] = {}; //core_req_tag_count by core req_tag_width
-	//tb->core_req_tag = 
-
-
-	for (int i = 0; i < 5; ++i){
-		//toggle the clock
-		tick(tb);
-	}
-
-	delete tb;
-	
-	exit(0);
-}
-

hw/unit_tests/cache/cachesim.cpp

@@ -0,0 +1,270 @@
+#include "cachesim.h"
+#include <fstream>
+#include <iomanip>
+#include <iostream>
+#include <vector>
+
+uint64_t timestamp = 0;
+
+double sc_time_stamp() { 
+  return timestamp;
+}
+
+CacheSim::CacheSim() {
+  // force random values for uninitialized signals  
+  Verilated::randReset(2);
+
+  ram_ = nullptr;
+  cache_ = new VVX_cache();
+
+  dram_rsp_active_ = false;
+  snp_req_active_ = false;
+
+//#ifdef VCD_OUTPUT
+  Verilated::traceEverOn(true);
+  trace_ = new VerilatedVcdC;
+  cache_->trace(trace_, 99);
+  trace_->open("trace.vcd");
+//#endif
+}
+
+CacheSim::~CacheSim() {
+//#ifdef VCD_OUTPUT
+  trace_->close();
+//#endif
+  delete cache_;
+}
+
+void CacheSim::attach_ram(RAM* ram) {
+  ram_ = ram;
+  dram_rsp_vec_.clear();
+}
+
+void CacheSim::reset() {
+#ifndef NDEBUG
+  std::cout << timestamp << ": [sim] reset()" << std::endl;
+#endif
+
+  cache_->reset = 1;
+  this->step();
+  cache_->reset = 0;
+  this->step();
+  dram_rsp_vec_.clear();
+  
+}
+
+void CacheSim::step() {
+  cache_->clk = 0;
+  this->eval();
+
+  cache_->clk = 1;
+  this->eval();
+
+  //this->eval_reqs();
+  //this->eval_rsps();
+  this->eval_dram_bus();
+}
+
+void CacheSim::eval() {
+  cache_->eval();
+//#ifdef VCD_OUTPUT
+  trace_->dump(timestamp);
+//#endif
+  ++timestamp;
+}
+
+void CacheSim::run(){
+#ifndef NDEBUG
+  std::cout << timestamp << ": [sim] run()" << std::endl;
+#endif
+  // reset the device
+  this->reset();
+  this->step();
+
+  // execute program
+  while (!core_reqq_.empty()) {
+
+    for(int i = 0; i < 10; ++i){
+      if(i == 1){
+        this->clear_req(); //invalidate reqs
+      }
+      this->step();
+    }
+
+  }
+}
+
+void CacheSim::clear_req(){
+  cache_->core_req_valid = 0; 
+}
+
+/*
+void CacheSim::send_req(core_req_t *req){
+  core_reqq_.push(req);
+}
+
+bool CacheSim::get_core_req_ready(){
+  return cache_->core_req_ready; 
+}
+
+bool CacheSim::get_core_rsp_ready(){
+  return cache_->core_rsp_ready; 
+}
+*/
+
+void CacheSim::set_core_req(){
+  cache_->core_req_valid = 0xf; 
+  cache_->core_req_rw = 0xf; 
+  cache_->core_req_byteen = 0xffff;   
+  cache_->core_req_addr[0] = 0x00;
+  cache_->core_req_addr[1] = 0xab;
+  cache_->core_req_addr[2] = 0xcd;
+  cache_->core_req_addr[3] = 0xe1;  
+  cache_->core_req_data[0] = 0xffffffff;
+  cache_->core_req_data[1] = 0x11111111;
+  cache_->core_req_data[2] = 0x22222222;
+  cache_->core_req_data[3] = 0x33333333;  
+  cache_->core_req_tag = 0xff;
+}
+
+void CacheSim::set_core_req2(){
+  cache_->core_req_valid = 0xf; //b1000
+  cache_->core_req_rw = 0x0; //b0000
+  cache_->core_req_byteen = 0xffff;   
+  cache_->core_req_addr[0] = 0x00;
+  cache_->core_req_addr[1] = 0xab;
+  cache_->core_req_addr[2] = 0xcd;
+  cache_->core_req_addr[3] = 0xe1;  
+  cache_->core_req_data[0] = 0x1111111;
+  cache_->core_req_data[1] = 0x4444444;
+  cache_->core_req_data[2] = 0x5555555;
+  cache_->core_req_data[3] = 0x6666666;
+  cache_->core_req_tag = 0xff;
+}
+
+
+void CacheSim::get_core_rsp(){
+  std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
+  std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
+  std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
+
+  char check = cache_->core_req_valid;
+   std::cout << "core_req_valid: " << check << std::endl;
+  std::cout << std::hex << "core_req_data: " << cache_->core_req_data << std::endl;
+  std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl; 
+}
+
+void CacheSim::get_dram_req(){
+  std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl;
+  std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl;
+  std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl;
+  std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl;
+  std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl; 
+  std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl;
+}
+
+void CacheSim::get_dram_rsp(){
+  std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl;
+  std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl; 
+  std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl;
+  std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
+}
+
+
+
+void CacheSim::eval_reqs(){
+  //check to see if cache is accepting reqs
+  /*if(!core_reqq_.empty() && cache_->core_req_ready){
+    core_req_t *req = core_reqq_.front();
+    cache_->core_req_valid = req->valid;
+    cache_->core_req_rw = req->rw; 
+    cache_->core_req_byteen = req->byteen;
+    cache_->core_req_addr = req->addr;
+    cache_->core_req_data = req->data;
+    cache_->core_req_tag = req->tag; 
+  }*/
+}
+
+void CacheSim::eval_rsps(){
+  //check to see if a request has been responded to
+  //if core_rsp tag equal to the front queue tag pop it from the queue
+  //while the req tag == rsp tag
+}
+
+void CacheSim::eval_dram_bus() {
+  if (ram_ == nullptr) {
+    cache_->dram_req_ready = 0;
+    return;
+  }
+
+  // schedule DRAM responses
+  int dequeue_index = -1;
+  for (int i = 0; i < dram_rsp_vec_.size(); i++) {
+    if (dram_rsp_vec_[i].cycles_left > 0) {
+      dram_rsp_vec_[i].cycles_left -= 1;
+    }
+    if ((dequeue_index == -1) 
+     && (dram_rsp_vec_[i].cycles_left == 0)) {
+      dequeue_index = i;
+    }
+  }
+
+  // send DRAM response  
+  if (dram_rsp_active_
+   && cache_->dram_rsp_valid 
+   && cache_->dram_rsp_ready) {
+    dram_rsp_active_ = false;
+  }
+  if (!dram_rsp_active_) {
+    if (dequeue_index != -1) { //time to respond to the request
+      cache_->dram_rsp_valid = 1;
+
+      //copy data from the rsp queue to the cache module
+      memcpy((uint8_t*)cache_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
+
+      cache_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;    
+      free(dram_rsp_vec_[dequeue_index].data); //take data out of the queue
+      dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
+      dram_rsp_active_ = true;
+    } else {
+      cache_->dram_rsp_valid = 0;
+    }
+  }
+
+  // handle DRAM stalls
+  bool dram_stalled = false;
+#ifdef ENABLE_DRAM_STALLS
+  if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { 
+    dram_stalled = true;
+  } else
+  if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) {
+    dram_stalled = true;
+  }
+#endif
+
+  // process DRAM requests
+  if (!dram_stalled) {
+    if (cache_->dram_req_valid) {
+      if (cache_->dram_req_rw) { //write = 1
+        uint64_t byteen = cache_->dram_req_byteen;
+        unsigned base_addr = (cache_->dram_req_addr * GLOBAL_BLOCK_SIZE);
+        uint8_t* data = (uint8_t*)(cache_->dram_req_data);
+        for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
+          if ((byteen >> i) & 0x1) {            
+            (*ram_)[base_addr + i] = data[i];
+          }
+        }
+      } else {
+        dram_req_t dram_req;
+        dram_req.cycles_left = DRAM_LATENCY;     
+        dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
+        dram_req.tag = cache_->dram_req_tag;
+        ram_->read(cache_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
+        dram_rsp_vec_.push_back(dram_req);
+      } 
+    }    
+  }
+
+  cache_->dram_req_ready = ~dram_stalled;
+}
+

hw/unit_tests/cache/cachesim.h

@@ -0,0 +1,89 @@
+#pragma once
+
+#include "VVX_cache.h"
+#include "VVX_cache__Syms.h"
+#include "verilated.h"
+
+//#ifdef VCD_OUTPUT
+#include <verilated_vcd_c.h>
+//#endif
+
+//#include <VX_config.h>
+#include "ram.h"
+#include <ostream>
+#include <vector>
+#include <queue>
+
+#define ENABLE_DRAM_STALLS
+#define DRAM_LATENCY 100
+#define DRAM_RQ_SIZE 16
+#define DRAM_STALLS_MODULO 16
+#define GLOBAL_BLOCK_SIZE 16
+
+typedef struct {
+  int cycles_left;
+  uint8_t *data;
+  unsigned tag;
+} dram_req_t;
+
+typedef struct {
+  bool valid = 1;
+  unsigned rw; 
+  unsigned byteen;
+  unsigned int *addr[4];
+  unsigned int *data[4];
+  unsigned tag;
+  bool responded; 
+} core_req_t;
+
+class CacheSim {
+public:
+  
+  CacheSim();
+  virtual ~CacheSim();
+  
+  bool busy();  
+
+  void reset();
+  void step();
+  void wait(uint32_t cycles); 
+  void attach_ram(RAM* ram);
+
+  void run();  //run until all reqs are empty
+  void clear_req(); 
+  void send_req(core_req_t *req);
+
+  void set_core_req();
+  void set_core_req2();
+
+  //display funcs
+
+  void get_dram_req();
+  void get_core_rsp();
+  bool get_core_req_ready();
+  bool get_core_rsp_ready();
+  void get_dram_rsp();
+
+
+private:  
+
+  void eval();  
+
+  void eval_reqs(); 
+  void eval_rsps();
+  void eval_dram_bus();
+  
+  std::queue<core_req_t*> core_reqq_; 
+  std::vector<dram_req_t> dram_rsp_vec_;
+  int dram_rsp_active_;
+
+  uint32_t snp_req_active_;
+  uint32_t snp_req_size_;
+  uint32_t pending_snp_reqs_;
+
+  VVX_cache *cache_;
+  RAM *ram_;
+//#ifdef VCD_OUTPUT
+  VerilatedVcdC *trace_;
+//#endif
+};

hw/unit_tests/cache/obj_dir/VVX_cache.mk

@@ -33,14 +33,15 @@ VM_PREFIX = VVX_cache
 VM_MODPREFIX = VVX_cache
 # User CFLAGS (from -CFLAGS on Verilator command line)
 VM_USER_CFLAGS = \
-	-std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \
+	-std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \
 
 # User LDLIBS (from -LDFLAGS on Verilator command line)
 VM_USER_LDLIBS = \
 
 # User .cpp files (from .cpp's on Verilator command line)
 VM_USER_CLASSES = \
-	cache_sim \
+	cachesim \
+	testbench \
 
 # User .cpp directories (from .cpp's on Verilator command line)
 VM_USER_DIR = \
@@ -56,7 +57,9 @@ include $(VERILATOR_ROOT)/include/verilated.mk
 ### Executable rules... (from --exe)
 VPATH += $(VM_USER_DIR)
 
-cache_sim.o: cache_sim.cpp
+cachesim.o: cachesim.cpp
+	$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
+testbench.o: testbench.cpp
 	$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
 
 ### Link rules... (from --exe)

hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp

@@ -0,0 +1,3 @@
+// DESCRIPTION: Generated by verilator_includer via makefile
+#define VL_INCLUDE_OPT include
+#include "VVX_cache.cpp"

hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d

@@ -0,0 +1,4 @@
+VVX_cache__ALLcls.o: VVX_cache__ALLcls.cpp VVX_cache.cpp VVX_cache.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h

hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp

@@ -0,0 +1,5 @@
+// DESCRIPTION: Generated by verilator_includer via makefile
+#define VL_INCLUDE_OPT include
+#include "VVX_cache__Trace.cpp"
+#include "VVX_cache__Syms.cpp"
+#include "VVX_cache__Trace__Slow.cpp"

hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d

@@ -0,0 +1,6 @@
+VVX_cache__ALLsup.o: VVX_cache__ALLsup.cpp VVX_cache__Trace.cpp \
+ /usr/local/share/verilator/include/verilated_vcd_c.h \
+ /usr/local/share/verilator/include/verilatedos.h \
+ /usr/local/share/verilator/include/verilated.h VVX_cache__Syms.h \
+ /usr/local/share/verilator/include/verilated_heavy.h VVX_cache.h \
+ VVX_cache__Syms.cpp VVX_cache__Trace__Slow.cpp

hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp

@@ -22,8 +22,6 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
     // Setup scopes
     __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue", "pfq_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
@@ -64,44 +62,4 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
     __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
     __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
-    __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
 }

hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h

@@ -27,8 +27,6 @@ class VVX_cache__Syms : public VerilatedSyms {
     // SCOPE NAMES
     VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue;
     VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue;
-    VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2;
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue;
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue;
@@ -69,46 +67,6 @@ class VVX_cache__Syms : public VerilatedSyms {
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2;
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue;
     VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue;
-    VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2;
     
     // CREATORS
     VVX_cache__Syms(VVX_cache* topp, const char* namep);

hw/unit_tests/cache/obj_dir/VVX_cache__ver.d

@@ -0,0 +1 @@
+obj_dir/VVX_cache.cpp obj_dir/VVX_cache.h obj_dir/VVX_cache.mk obj_dir/VVX_cache__Syms.cpp obj_dir/VVX_cache__Syms.h obj_dir/VVX_cache__Trace.cpp obj_dir/VVX_cache__Trace__Slow.cpp obj_dir/VVX_cache__ver.d obj_dir/VVX_cache_classes.mk  : /usr/local/bin/verilator_bin ../../rtl//VX_config.vh ../../rtl//VX_define.vh ../../rtl//VX_scope.vh ../../rtl//VX_user_config.vh ../../rtl/cache/VX_bank.v ../../rtl/cache/VX_bank_core_req_arb.v ../../rtl/cache/VX_cache.v ../../rtl/cache/VX_cache_config.vh ../../rtl/cache/VX_cache_core_req_bank_sel.v ../../rtl/cache/VX_cache_core_rsp_merge.v ../../rtl/cache/VX_cache_dram_fill_arb.v ../../rtl/cache/VX_cache_dram_req_arb.v ../../rtl/cache/VX_cache_miss_resrv.v ../../rtl/cache/VX_prefetcher.v ../../rtl/cache/VX_snp_forwarder.v ../../rtl/cache/VX_snp_rsp_arb.v ../../rtl/cache/VX_tag_data_access.v ../../rtl/cache/VX_tag_data_structure.v ../../rtl/libs/VX_fair_arbiter.v ../../rtl/libs/VX_fixed_arbiter.v ../../rtl/libs/VX_generic_queue.v ../../rtl/libs/VX_generic_register.v ../../rtl/libs/VX_indexable_queue.v ../../rtl/libs/VX_priority_encoder.v /usr/local/bin/verilator_bin 

hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat

@@ -0,0 +1,37 @@
+# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
+C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp"
+S      6992  4983715  1593571269   845187304  1593571269   845187304 "../../rtl//VX_config.vh"
+S      8927  4983721  1593571269   845187304  1593571269   845187304 "../../rtl//VX_define.vh"
+S     16028  4983736  1593571269   849188141  1593571269   849188141 "../../rtl//VX_scope.vh"
+S       147  4980795  1592347024   921834494  1592347024   921834494 "../../rtl//VX_user_config.vh"
+S     34555  4983741  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_bank.v"
+S      6128  4983742  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_bank_core_req_arb.v"
+S     22942  4985366  1594500482   317211549  1594500482   317211549 "../../rtl/cache/VX_cache.v"
+S      2842  4983744  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_cache_config.vh"
+S      1745  4983745  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v"
+S      3719  4983746  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_cache_core_rsp_merge.v"
+S      3602  4983747  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v"
+S      4396  4985343  1593571951    15994059  1593571951     7993214 "../../rtl/cache/VX_cache_dram_req_arb.v"
+S      7305  4983749  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_cache_miss_resrv.v"
+S      1996  4983748  1593571988   408039126  1593571988   396037801 "../../rtl/cache/VX_prefetcher.v"
+S      5064  4983751  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_snp_forwarder.v"
+S      1210  4983752  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_snp_rsp_arb.v"
+S      8840  4983753  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_tag_data_access.v"
+S      3211  4983754  1593571269   849188141  1593571269   849188141 "../../rtl/cache/VX_tag_data_structure.v"
+S      1865  4983777  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_fair_arbiter.v"
+S      1022  4983778  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_fixed_arbiter.v"
+S      5974  4983779  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_generic_queue.v"
+S       582  4983780  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_generic_register.v"
+S      1552  4983782  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_indexable_queue.v"
+S       491  4983785  1593571269   849188141  1593571269   849188141 "../../rtl/libs/VX_priority_encoder.v"
+S   8183216  2503059  1591812755   756668753  1591812755   756668753 "/usr/local/bin/verilator_bin"
+T   3001929  4983824  1594500491   517601979  1594500491   517601979 "obj_dir/VVX_cache.cpp"
+T     93468  4983825  1594500491   473600112  1594500491   473600112 "obj_dir/VVX_cache.h"
+T      2104  4983826  1594500491   517601979  1594500491   517601979 "obj_dir/VVX_cache.mk"
+T      8694  4983827  1594500491   449599094  1594500491   449599094 "obj_dir/VVX_cache__Syms.cpp"
+T      4866  4983828  1594500491   449599094  1594500491   449599094 "obj_dir/VVX_cache__Syms.h"
+T    429460  4983829  1594500491   469599943  1594500491   469599943 "obj_dir/VVX_cache__Trace.cpp"
+T    700979  4983830  1594500491   461599603  1594500491   461599603 "obj_dir/VVX_cache__Trace__Slow.cpp"
+T      1118  4980960  1594500491   517601979  1594500491   517601979 "obj_dir/VVX_cache__ver.d"
+T         0        0  1594500491   517601979  1594500491   517601979 "obj_dir/VVX_cache__verFiles.dat"
+T      1315  4983831  1594500491   517601979  1594500491   517601979 "obj_dir/VVX_cache_classes.mk"

hw/unit_tests/cache/obj_dir/cache_sim.d

@@ -0,0 +1,6 @@
+cache_sim.o: ../cache_sim.cpp VVX_cache.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
+ VVX_cache.h /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_vcd_c.h

hw/unit_tests/cache/obj_dir/cachesim.d

@@ -0,0 +1,6 @@
+cachesim.o: ../cachesim.cpp ../cachesim.h VVX_cache.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
+ VVX_cache.h /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

hw/unit_tests/cache/obj_dir/testbench.d

@@ -0,0 +1,6 @@
+testbench.o: ../testbench.cpp ../cachesim.h VVX_cache.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
+ VVX_cache.h /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

hw/unit_tests/cache/obj_dir/verilated.d

@@ -0,0 +1,8 @@
+verilated.o: /usr/local/share/verilator/include/verilated.cpp \
+ /usr/local/share/verilator/include/verilatedos.h \
+ /usr/local/share/verilator/include/verilated_imp.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated_syms.h \
+ /usr/local/share/verilator/include/verilated_sym_props.h \
+ /usr/local/share/verilator/include/verilated_config.h

hw/unit_tests/cache/obj_dir/verilated_vcd_c.d

@@ -0,0 +1,4 @@
+verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \
+ /usr/local/share/verilator/include/verilatedos.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_vcd_c.h

hw/unit_tests/cache/ram.h

@@ -0,0 +1,64 @@
+#pragma once
+
+#include <stdio.h>
+#include <stdint.h>
+
+class RAM {
+private:
+
+  mutable uint8_t *mem_[(1 << 12)];      
+
+  uint8_t *get(uint32_t address) const {
+    uint32_t block_addr   = address >> 20;
+    uint32_t block_offset = address & 0x000FFFFF;
+    if (mem_[block_addr] == NULL) {
+      mem_[block_addr] = new uint8_t[(1 << 20)];
+    }
+    return mem_[block_addr] + block_offset;
+  }
+
+public:
+
+  RAM() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      mem_[i] = NULL;
+    }
+  }
+
+  ~RAM() {
+    this->clear();
+  }
+
+  size_t size() const {
+    return (1ull << 32);
+  }
+
+  void clear() {
+    for (uint32_t i = 0; i < (1 << 12); i++) {
+      if (mem_[i]) {
+        delete mem_[i];
+        mem_[i] = NULL;
+      }
+    }
+  }
+
+  void read(uint32_t address, uint32_t length, uint8_t *data) const {
+    for (unsigned i = 0; i < length; i++) {
+      data[i] = *this->get(address + i);
+    }
+  }
+
+  void write(uint32_t address, uint32_t length, const uint8_t *data) {
+    for (unsigned i = 0; i < length; i++) {
+      *this->get(address + i) = data[i];
+    }
+  }
+
+  uint8_t& operator[](uint32_t address) {
+    return *get(address);
+  }
+
+  const uint8_t& operator[](uint32_t address) const {
+    return *get(address);
+  }
+};

hw/unit_tests/cache/simulator.cpp

@@ -1,83 +0,0 @@
-#include "simulator.h"
-#include <iostream>
-#include <fstream>
-#include <iomanip>
-
-uint64_t timestamp = 0;
-
-double sc_time_stamp() { 
-  return timestamp;
-}
-
-Simulator::Simulator() {    
-  // force random values for unitialized signals  
-  Verilated::randReset(1);
-
-  vortex_ = new VVX_priority_encoder();
-
-#ifdef VCD_OUTPUT
-  Verilated::traceEverOn(true);
-  trace_ = new VerilatedVcdC;
-  vortex_->trace(trace_, 99);
-  trace_->open("trace.vcd");
-#endif  
-}
-
-Simulator::~Simulator() {
-#ifdef VCD_OUTPUT
-  trace_->close();
-#endif
-  delete vortex_;
-}
-
-
-
-void Simulator::step() {
-  this->eval();
-
-  this->eval();
-}
-
-
-void Simulator::reset() {     
-#ifndef NDEBUG
-  std::cout << timestamp << ": [sim] reset()" << std::endl;
-#endif
-
-  this->step();  
-}
-
-
-void Simulator::eval() {
-  vortex_->eval();
-#ifdef VCD_OUTPUT
-  trace_->dump(timestamp);
-#endif
-   ++timestamp;
-}
-
-void Simulator::wait(uint32_t cycles) {
-  for (int i = 0; i < cycles; ++i) {
-    this->step();
-  }
-}
-
-
-
-bool Simulator::run() {
-  // reset the device
-  this->reset();
-
-  // execute program
-  this->step();
-  
-
-  // wait 5 cycles to flush the pipeline
-  this->wait(5);
-
-
-
-  return 0;
-}
-
-

hw/unit_tests/cache/simulator.h

@@ -1,52 +0,0 @@
-#pragma once
-
-#include "VVX_priority_encoder.h"
-#include "VVX_priority_encoder__Syms.h"
-#include "verilated.h"
-
-#ifdef VCD_OUTPUT
-#include <verilated_vcd_c.h>
-#endif
-
-//#include <VX_config.h>
-
-#include <ostream>
-#include <vector>
-
-class Simulator {
-public:
-  
-  Simulator();
-  virtual ~Simulator();
-
-  void load_bin(const char* program_file);
-  void load_ihex(const char* program_file);
-  
-  bool is_busy();  
-
-  void reset();
-  void step();
-  void wait(uint32_t cycles);
-  void flush_caches(uint32_t mem_addr, uint32_t size);  
-
-
-  bool run();  
-  void print_stats(std::ostream& out);
-
-private:  
-
-  void eval();  
-
-  void eval_dram_bus();
-  void eval_io_bus();
-  void eval_snp_bus();
-
-  uint32_t snp_req_active_;
-  uint32_t snp_req_size_;
-  uint32_t pending_snp_reqs_;
-
-  VVX_priority_encoder *vortex_;
-#ifdef VCD_OUTPUT
-  VerilatedVcdC *trace_;
-#endif
-};

hw/unit_tests/cache/testbase.cpp

@@ -1,59 +0,0 @@
-#include "VVX_generic_queue.h"
-#include "VVX_generic_queue__Syms.h"
-#include "verilated.h"
-
-#include <verilated_vcd_c.h>
-
-#include <iostream>
-#include <vector>
-
-uint64_t timestamp = 0;
-
-double sc_time_stamp() { 
-  return timestamp;
-}
-
-int main(int argc, char **argv){
-	Verilated::commandArgs(argc, argv); //passes the command args to the object
-
-	VVX_generic_queue *tb = new VVX_generic_queue;
-	tb->reset = 1; 
-	tb->eval(); 
-	tb->reset = 0; 
-	unsigned int clk;
-	bool full;
-	bool empty;
-	int size; 
-	int data_out; 
-	tb->data_in = 0xff; 
-	
-	tb->push = 1; 
-
-	for (int i = 0; i < 5; ++i){
-		//toggle the clock
-		tb->eval();
-		tb->clk = 1; 
-
-		tb->eval();
-		tb->clk = 0;
-		tb->eval();
-
-
-		full = tb->full; 
-		empty = tb->empty;
-		size = tb->size;
-		data_out = tb->data_out;
-		clk = tb->clk; 
-
-		std::cout << "clk: " << clk << std::endl; 
-		std::cout << "data_out: " << data_out << std::endl; 
-		std::cout << "empty: " << empty << std::endl; 
-		std::cout << "full: " << full << std::endl; 
-		std::cout << "size: " << size << std::endl; 
-		
-	}
-
-	delete tb;
-	
-	exit(0);
-}

hw/unit_tests/cache/testbench.cpp

@@ -1,12 +1,53 @@
-#include "simulator.h"
+#include "cachesim.h"
 #include <iostream>
 #include <fstream>
 #include <iomanip>
 
+#define VCD_OUTPUT 1
+
 int main(int argc, char **argv)
 {
-	Simulator simulator;
+  //init
-	bool curr = simulator.run();
+  RAM ram;
+	CacheSim cachesim;
+  cachesim.attach_ram(&ram);
   
+  
+	// reset the device
+  cachesim.reset();
+
+  //write block to cache
+  cachesim.set_core_req();
+
+  for (int i = 0; i < 100; ++i){
+    /*if(i == 1){
+      cachesim.clear_req();
+    }*/
+    cachesim.step();
+    cachesim.get_core_rsp();
+  }
+  
+  // read block
+  cachesim.set_core_req2();
+  for (int i = 0; i < 100; ++i){
+    /*if(i == 1){
+      //read block from cache
+      cachesim.clear_req();
+
+    }*/
+    cachesim.step();
+    cachesim.get_core_rsp();
+  } 
+  
+  /*
+  core_req_t *write;
+  write->valid = 1;
+  //write.tag = 0xff; //TODO: make a reasonable tag
+  //write.addr[0] = 0x11111111; 
+  //write.addr[1] = 0x22222222;
+  //write.addr[2] = 0x33333333;
+  //write.addr[3] = 0x44444444;
+  //write.
+  */
 	return 0;
 }