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trmontgomery
270
hw/unit_tests/cache/cachesim.cpp
vendored
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270
hw/unit_tests/cache/cachesim.cpp
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#include "cachesim.h"
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#include <fstream>
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#include <iomanip>
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#include <iostream>
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#include <vector>
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uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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CacheSim::CacheSim() {
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// force random values for uninitialized signals
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Verilated::randReset(2);
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ram_ = nullptr;
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cache_ = new VVX_cache();
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dram_rsp_active_ = false;
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snp_req_active_ = false;
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//#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC;
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cache_->trace(trace_, 99);
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trace_->open("trace.vcd");
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//#endif
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}
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CacheSim::~CacheSim() {
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//#ifdef VCD_OUTPUT
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trace_->close();
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//#endif
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delete cache_;
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}
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void CacheSim::attach_ram(RAM* ram) {
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ram_ = ram;
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dram_rsp_vec_.clear();
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}
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void CacheSim::reset() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] reset()" << std::endl;
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#endif
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cache_->reset = 1;
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this->step();
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cache_->reset = 0;
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this->step();
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dram_rsp_vec_.clear();
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}
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void CacheSim::step() {
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cache_->clk = 0;
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this->eval();
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cache_->clk = 1;
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this->eval();
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//this->eval_reqs();
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//this->eval_rsps();
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this->eval_dram_bus();
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}
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void CacheSim::eval() {
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cache_->eval();
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//#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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//#endif
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++timestamp;
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}
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void CacheSim::run(){
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] run()" << std::endl;
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#endif
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// reset the device
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this->reset();
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this->step();
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// execute program
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while (!core_reqq_.empty()) {
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for(int i = 0; i < 10; ++i){
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if(i == 1){
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this->clear_req(); //invalidate reqs
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}
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this->step();
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}
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}
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}
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void CacheSim::clear_req(){
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cache_->core_req_valid = 0;
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}
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/*
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void CacheSim::send_req(core_req_t *req){
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core_reqq_.push(req);
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}
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bool CacheSim::get_core_req_ready(){
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return cache_->core_req_ready;
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}
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bool CacheSim::get_core_rsp_ready(){
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return cache_->core_rsp_ready;
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}
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*/
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void CacheSim::set_core_req(){
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cache_->core_req_valid = 0xf;
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cache_->core_req_rw = 0xf;
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cache_->core_req_byteen = 0xffff;
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cache_->core_req_addr[0] = 0x00;
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cache_->core_req_addr[1] = 0xab;
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cache_->core_req_addr[2] = 0xcd;
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cache_->core_req_addr[3] = 0xe1;
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cache_->core_req_data[0] = 0xffffffff;
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cache_->core_req_data[1] = 0x11111111;
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cache_->core_req_data[2] = 0x22222222;
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cache_->core_req_data[3] = 0x33333333;
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cache_->core_req_tag = 0xff;
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}
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void CacheSim::set_core_req2(){
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cache_->core_req_valid = 0xf; //b1000
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cache_->core_req_rw = 0x0; //b0000
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cache_->core_req_byteen = 0xffff;
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cache_->core_req_addr[0] = 0x00;
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cache_->core_req_addr[1] = 0xab;
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cache_->core_req_addr[2] = 0xcd;
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cache_->core_req_addr[3] = 0xe1;
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cache_->core_req_data[0] = 0x1111111;
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cache_->core_req_data[1] = 0x4444444;
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cache_->core_req_data[2] = 0x5555555;
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cache_->core_req_data[3] = 0x6666666;
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cache_->core_req_tag = 0xff;
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}
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void CacheSim::get_core_rsp(){
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std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
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std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
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std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
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char check = cache_->core_req_valid;
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std::cout << "core_req_valid: " << check << std::endl;
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std::cout << std::hex << "core_req_data: " << cache_->core_req_data << std::endl;
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std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl;
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}
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void CacheSim::get_dram_req(){
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std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl;
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std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl;
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std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl;
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std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl;
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std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl;
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std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl;
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}
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void CacheSim::get_dram_rsp(){
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std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl;
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std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl;
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std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl;
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std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
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}
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void CacheSim::eval_reqs(){
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//check to see if cache is accepting reqs
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/*if(!core_reqq_.empty() && cache_->core_req_ready){
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core_req_t *req = core_reqq_.front();
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cache_->core_req_valid = req->valid;
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cache_->core_req_rw = req->rw;
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cache_->core_req_byteen = req->byteen;
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cache_->core_req_addr = req->addr;
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cache_->core_req_data = req->data;
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cache_->core_req_tag = req->tag;
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}*/
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}
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void CacheSim::eval_rsps(){
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//check to see if a request has been responded to
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//if core_rsp tag equal to the front queue tag pop it from the queue
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//while the req tag == rsp tag
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}
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void CacheSim::eval_dram_bus() {
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if (ram_ == nullptr) {
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cache_->dram_req_ready = 0;
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return;
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}
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// schedule DRAM responses
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int dequeue_index = -1;
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for (int i = 0; i < dram_rsp_vec_.size(); i++) {
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if (dram_rsp_vec_[i].cycles_left > 0) {
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dram_rsp_vec_[i].cycles_left -= 1;
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}
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if ((dequeue_index == -1)
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&& (dram_rsp_vec_[i].cycles_left == 0)) {
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dequeue_index = i;
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}
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}
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// send DRAM response
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if (dram_rsp_active_
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&& cache_->dram_rsp_valid
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&& cache_->dram_rsp_ready) {
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dram_rsp_active_ = false;
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}
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if (!dram_rsp_active_) {
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if (dequeue_index != -1) { //time to respond to the request
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cache_->dram_rsp_valid = 1;
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//copy data from the rsp queue to the cache module
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memcpy((uint8_t*)cache_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE);
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cache_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag;
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free(dram_rsp_vec_[dequeue_index].data); //take data out of the queue
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dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index);
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dram_rsp_active_ = true;
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} else {
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cache_->dram_rsp_valid = 0;
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}
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}
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// handle DRAM stalls
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bool dram_stalled = false;
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#ifdef ENABLE_DRAM_STALLS
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if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) {
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dram_stalled = true;
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} else
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if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) {
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dram_stalled = true;
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}
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#endif
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// process DRAM requests
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if (!dram_stalled) {
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if (cache_->dram_req_valid) {
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if (cache_->dram_req_rw) { //write = 1
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uint64_t byteen = cache_->dram_req_byteen;
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unsigned base_addr = (cache_->dram_req_addr * GLOBAL_BLOCK_SIZE);
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uint8_t* data = (uint8_t*)(cache_->dram_req_data);
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for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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} else {
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dram_req_t dram_req;
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dram_req.cycles_left = DRAM_LATENCY;
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dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE);
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dram_req.tag = cache_->dram_req_tag;
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ram_->read(cache_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data);
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dram_rsp_vec_.push_back(dram_req);
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}
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}
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}
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cache_->dram_req_ready = ~dram_stalled;
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}
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