more renaming and cleanup
This commit is contained in:
Richard Yan
685
lib/include/VX_config.h
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685
lib/include/VX_config.h
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@@ -0,0 +1,685 @@
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// auto-generated by gen_config.py. DO NOT EDIT
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// Generated at 2024-05-07 13:55:58.398687
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// Translated from ./rtl/VX_config.vh:
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
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||||
//
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||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
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||||
|
||||
#ifndef VX_CONFIG_VH
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||||
#define VX_CONFIG_VH
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||||
|
||||
#ifndef MIN
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||||
#define MIN(x, y) (((x) < (y)) ? (x) : (y))
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||||
#endif
|
||||
|
||||
#ifndef MAX
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||||
#define MAX(x, y) (((x) > (y)) ? (x) : (y))
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||||
#endif
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||||
|
||||
#ifndef CLAMP
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||||
#define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x)))
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||||
#endif
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||||
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||||
#ifndef UP
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#define UP(x) (((x) != 0) ? (x) : 1)
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||||
#endif
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||||
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||||
///////////////////////////////////////////////////////////////////////////////
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||||
|
||||
#ifndef EXT_M_DISABLE
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||||
#define EXT_M_ENABLE
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||||
#endif
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||||
|
||||
#ifndef EXT_F_DISABLE
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||||
#define EXT_F_ENABLE
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||||
#endif
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||||
|
||||
#ifndef XLEN_32
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||||
#ifndef XLEN_64
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||||
#define XLEN_32
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#endif
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||||
#endif
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||||
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||||
#ifdef XLEN_64
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#define XLEN 64
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#endif
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||||
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||||
#ifdef XLEN_32
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#define XLEN 32
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||||
#endif
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||||
|
||||
#ifdef EXT_D_ENABLE
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||||
#define FLEN_64
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#else
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#define FLEN_32
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#endif
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#ifdef FLEN_64
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#define FLEN 64
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#endif
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||||
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#ifdef FLEN_32
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#define FLEN 32
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#endif
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||||
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#ifdef XLEN_64
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#ifdef FLEN_32
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#define FPU_RV64F
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#endif
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#endif
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|
||||
#ifndef NUM_CLUSTERS
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#define NUM_CLUSTERS 1
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#endif
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||||
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#ifndef NUM_CORES
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#define NUM_CORES 8
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#endif
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#ifndef NUM_WARPS
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#define NUM_WARPS 8
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#endif
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#ifndef NUM_THREADS
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#define NUM_THREADS 8
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#endif
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#ifndef NUM_BARRIERS
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#define NUM_BARRIERS 8
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#endif
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#ifndef SOCKET_SIZE
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#define SOCKET_SIZE MIN(4, NUM_CORES)
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#endif
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#define NUM_SOCKETS UP(NUM_CORES / SOCKET_SIZE)
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#ifdef L2_ENABLE
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#define L2_ENABLED 1
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#else
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#define L2_ENABLED 0
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#endif
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#ifdef L3_ENABLE
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#define L3_ENABLED 1
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#else
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#define L3_ENABLED 0
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#endif
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|
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#ifdef L1_DISABLE
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#define ICACHE_DISABLE
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#define DCACHE_DISABLE
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#endif
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||||
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#ifndef MEM_BLOCK_SIZE
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#define MEM_BLOCK_SIZE 64
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#endif
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||||
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#ifndef MEM_ADDR_WIDTH
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||||
#ifdef XLEN_64
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#define MEM_ADDR_WIDTH 48
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||||
#else
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#define MEM_ADDR_WIDTH 32
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||||
#endif
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||||
#endif
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||||
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||||
#ifndef L1_LINE_SIZE
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||||
#ifdef L1_DISABLE
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||||
#define L1_LINE_SIZE ((L2_ENABLED || L3_ENABLED) ? 4 : MEM_BLOCK_SIZE)
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||||
#else
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||||
#define L1_LINE_SIZE ((L2_ENABLED || L3_ENABLED) ? 16 : MEM_BLOCK_SIZE)
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||||
#endif
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||||
#endif
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||||
|
||||
#ifdef L2_ENABLE
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||||
#define L2_LINE_SIZE MEM_BLOCK_SIZE
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||||
#else
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||||
#define L2_LINE_SIZE L1_LINE_SIZE
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||||
#endif
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||||
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||||
#ifdef L3_ENABLE
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#define L3_LINE_SIZE MEM_BLOCK_SIZE
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||||
#else
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||||
#define L3_LINE_SIZE L2_LINE_SIZE
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||||
#endif
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||||
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#ifdef XLEN_64
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#ifndef STARTUP_ADDR
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#define STARTUP_ADDR 0x180000000
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#endif
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#ifndef STACK_BASE_ADDR
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#define STACK_BASE_ADDR 0x1FF000000
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#endif
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#else
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#ifndef STARTUP_ADDR
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#define STARTUP_ADDR 0x80000000
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#endif
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#ifndef STACK_BASE_ADDR
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#define STACK_BASE_ADDR 0xFF000000
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#endif
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#endif
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#ifndef SMEM_BASE_ADDR
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#define SMEM_BASE_ADDR STACK_BASE_ADDR
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#endif
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#ifndef SMEM_LOG_SIZE
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#define SMEM_LOG_SIZE 19
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#endif
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#ifndef IO_BASE_ADDR
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#define IO_BASE_ADDR (SMEM_BASE_ADDR + (1 << SMEM_LOG_SIZE))
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#endif
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#ifndef IO_COUT_ADDR
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#define IO_COUT_ADDR IO_BASE_ADDR
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#endif
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#define IO_COUT_SIZE MEM_BLOCK_SIZE
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#ifndef IO_CSR_ADDR
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#define IO_CSR_ADDR (IO_COUT_ADDR + IO_COUT_SIZE)
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#endif
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||||
#define IO_CSR_SIZE (4 * 64 * NUM_CORES * NUM_CLUSTERS)
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||||
#ifndef STACK_LOG2_SIZE
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#define STACK_LOG2_SIZE 13
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#endif
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||||
#define STACK_SIZE (1 << STACK_LOG2_SIZE)
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||||
|
||||
#define RESET_DELAY 8
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||||
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||||
#ifndef STALL_TIMEOUT
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||||
#define STALL_TIMEOUT (100000 * (1 ** (L2_ENABLED + L3_ENABLED)))
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||||
#endif
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||||
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||||
#ifndef SV_DPI
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||||
#define DPI_DISABLE
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||||
#endif
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||||
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||||
#ifndef FPU_FPNEW
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||||
#ifndef FPU_DSP
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#ifndef FPU_DPI
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#ifndef SYNTHESIS
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#ifndef DPI_DISABLE
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#define FPU_DPI
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#else
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#define FPU_DSP
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#endif
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#else
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#define FPU_DSP
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#endif
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#endif
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||||
#endif
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#endif
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#ifndef SYNTHESIS
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#ifndef DPI_DISABLE
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#define IMUL_DPI
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#define IDIV_DPI
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#endif
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#endif
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#ifndef DEBUG_LEVEL
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#define DEBUG_LEVEL 3
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#endif
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// Pipeline Configuration /////////////////////////////////////////////////////
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// Issue width
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#ifndef ISSUE_WIDTH
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#define ISSUE_WIDTH NUM_WARPS
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#endif
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// Number of ALU units
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#ifndef NUM_ALU_LANES
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#define NUM_ALU_LANES NUM_THREADS
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#endif
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#ifndef NUM_ALU_BLOCKS
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#define NUM_ALU_BLOCKS 4
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#endif
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// Number of FPU units
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#ifndef NUM_FPU_LANES
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#define NUM_FPU_LANES NUM_THREADS
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#endif
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#ifndef NUM_FPU_BLOCKS
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#define NUM_FPU_BLOCKS 2
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#endif
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// Number of LSU units
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#ifndef NUM_LSU_LANES
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#define NUM_LSU_LANES NUM_THREADS
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#endif
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// Number of SFU units
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#ifndef NUM_SFU_LANES
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#define NUM_SFU_LANES MIN(NUM_THREADS, 4)
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#endif
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// Size of Instruction Buffer
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#ifndef IBUF_SIZE
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#define IBUF_SIZE (4 * ISSUE_WIDTH)
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#endif
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// Size of LSU Request Queue
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#ifndef LSUQ_SIZE
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#define LSUQ_SIZE (4 * NUM_WARPS * (NUM_THREADS / NUM_LSU_LANES))
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#endif
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// LSU Duplicate Address Check
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#ifndef LSU_DUP_DISABLE
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#define LSU_DUP_ENABLE
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#endif
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#ifdef LSU_DUP_ENABLE
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#define LSU_DUP_ENABLED 1
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#else
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#define LSU_DUP_ENABLED 0
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#endif
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#ifdef GBAR_ENABLE
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#define GBAR_ENABLED 1
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#else
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#define GBAR_ENABLED 0
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#endif
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#ifndef LATENCY_IMUL
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#ifdef VIVADO
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#define LATENCY_IMUL 4
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#endif
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#ifdef QUARTUS
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#define LATENCY_IMUL 3
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#endif
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#ifndef LATENCY_IMUL
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#define LATENCY_IMUL 4
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#endif
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#endif
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// Floating-Point Units ///////////////////////////////////////////////////////
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// Size of FPU Request Queue
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#ifndef FPUQ_SIZE
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#define FPUQ_SIZE (2 * (NUM_THREADS / NUM_FPU_LANES))
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#endif
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// FNCP Latency
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#ifndef LATENCY_FNCP
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#define LATENCY_FNCP 2
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#endif
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// FMA Latency
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#ifndef LATENCY_FMA
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#ifdef FPU_DPI
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#define LATENCY_FMA 4
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#endif
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#ifdef FPU_FPNEW
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#define LATENCY_FMA 4
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#endif
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#ifdef FPU_DSP
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#ifdef QUARTUS
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#define LATENCY_FMA 4
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#endif
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#ifdef VIVADO
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#define LATENCY_FMA 16
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#endif
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#ifndef LATENCY_FMA
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#define LATENCY_FMA 4
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#endif
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#endif
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#endif
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// FDIV Latency
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#ifndef LATENCY_FDIV
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#ifdef FPU_DPI
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#define LATENCY_FDIV 15
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#endif
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#ifdef FPU_FPNEW
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#define LATENCY_FDIV 16
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#endif
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#ifdef FPU_DSP
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#ifdef QUARTUS
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#define LATENCY_FDIV 15
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#endif
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#ifdef VIVADO
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#define LATENCY_FDIV 28
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#endif
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#ifndef LATENCY_FDIV
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#define LATENCY_FDIV 16
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||||
#endif
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||||
#endif
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||||
#endif
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||||
|
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// FSQRT Latency
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||||
#ifndef LATENCY_FSQRT
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||||
#ifdef FPU_DPI
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||||
#define LATENCY_FSQRT 10
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||||
#endif
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||||
#ifdef FPU_FPNEW
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||||
#define LATENCY_FSQRT 16
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||||
#endif
|
||||
#ifdef FPU_DSP
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||||
#ifdef QUARTUS
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||||
#define LATENCY_FSQRT 10
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||||
#endif
|
||||
#ifdef VIVADO
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||||
#define LATENCY_FSQRT 28
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||||
#endif
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||||
#ifndef LATENCY_FSQRT
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||||
#define LATENCY_FSQRT 16
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||||
#endif
|
||||
#endif
|
||||
#endif
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||||
|
||||
// FCVT Latency
|
||||
#ifndef LATENCY_FCVT
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||||
#define LATENCY_FCVT 5
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#endif
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||||
|
||||
// Icache Configurable Knobs //////////////////////////////////////////////////
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||||
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||||
// Cache Enable
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||||
#ifndef ICACHE_DISABLE
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||||
#define ICACHE_ENABLE
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||||
#endif
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||||
#ifdef ICACHE_ENABLE
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||||
#define ICACHE_ENABLED 1
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||||
#else
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||||
#define ICACHE_ENABLED 0
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||||
#define NUM_ICACHES 0
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||||
#endif
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||||
|
||||
// Number of Cache Units
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||||
#ifndef NUM_ICACHES
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||||
#define NUM_ICACHES UP(SOCKET_SIZE / 4)
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||||
#endif
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||||
|
||||
// Cache Size
|
||||
#ifndef ICACHE_SIZE
|
||||
#define ICACHE_SIZE 16384
|
||||
#endif
|
||||
|
||||
// Core Response Queue Size
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||||
#ifndef ICACHE_CRSQ_SIZE
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||||
#define ICACHE_CRSQ_SIZE 2
|
||||
#endif
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||||
|
||||
// Miss Handling Register Size
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||||
#ifndef ICACHE_MSHR_SIZE
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||||
#define ICACHE_MSHR_SIZE 16
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||||
#endif
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||||
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||||
// Memory Request Queue Size
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||||
#ifndef ICACHE_MREQ_SIZE
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||||
#define ICACHE_MREQ_SIZE 4
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||||
#endif
|
||||
|
||||
// Memory Response Queue Size
|
||||
#ifndef ICACHE_MRSQ_SIZE
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||||
#define ICACHE_MRSQ_SIZE 0
|
||||
#endif
|
||||
|
||||
// Number of Associative Ways
|
||||
#ifndef ICACHE_NUM_WAYS
|
||||
#define ICACHE_NUM_WAYS 1
|
||||
#endif
|
||||
|
||||
// Dcache Configurable Knobs //////////////////////////////////////////////////
|
||||
|
||||
// Cache Enable
|
||||
#ifndef DCACHE_DISABLE
|
||||
#define DCACHE_ENABLE
|
||||
#endif
|
||||
#ifdef DCACHE_ENABLE
|
||||
#define DCACHE_ENABLED 1
|
||||
#else
|
||||
#define DCACHE_ENABLED 0
|
||||
#define NUM_DCACHES 0
|
||||
#define DCACHE_NUM_BANKS 1
|
||||
#endif
|
||||
|
||||
// Number of Cache Units
|
||||
#ifndef NUM_DCACHES
|
||||
#define NUM_DCACHES UP(SOCKET_SIZE / 4)
|
||||
#endif
|
||||
|
||||
// Cache Size
|
||||
#ifndef DCACHE_SIZE
|
||||
#define DCACHE_SIZE 16384
|
||||
#endif
|
||||
|
||||
// Number of Banks
|
||||
#ifndef DCACHE_NUM_BANKS
|
||||
#define DCACHE_NUM_BANKS NUM_LSU_LANES
|
||||
#endif
|
||||
|
||||
// Core Response Queue Size
|
||||
#ifndef DCACHE_CRSQ_SIZE
|
||||
#define DCACHE_CRSQ_SIZE 2
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef DCACHE_MSHR_SIZE
|
||||
#define DCACHE_MSHR_SIZE 8
|
||||
#endif
|
||||
|
||||
// Memory Request Queue Size
|
||||
#ifndef DCACHE_MREQ_SIZE
|
||||
#define DCACHE_MREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Memory Response Queue Size
|
||||
#ifndef DCACHE_MRSQ_SIZE
|
||||
#define DCACHE_MRSQ_SIZE 0
|
||||
#endif
|
||||
|
||||
// Number of Associative Ways
|
||||
#ifndef DCACHE_NUM_WAYS
|
||||
#define DCACHE_NUM_WAYS 1
|
||||
#endif
|
||||
|
||||
// SM Configurable Knobs //////////////////////////////////////////////////////
|
||||
|
||||
#ifndef SM_DISABLE
|
||||
#define SM_ENABLE
|
||||
#endif
|
||||
|
||||
#ifdef SM_ENABLE
|
||||
#define SM_ENABLED 1
|
||||
#else
|
||||
#define SM_ENABLED 0
|
||||
#define SMEM_NUM_BANKS 1
|
||||
#endif
|
||||
|
||||
// Number of Banks
|
||||
#ifndef SMEM_NUM_BANKS
|
||||
#define SMEM_NUM_BANKS (NUM_LSU_LANES)
|
||||
#endif
|
||||
|
||||
// L2cache Configurable Knobs /////////////////////////////////////////////////
|
||||
|
||||
// Cache Size
|
||||
#ifndef L2_CACHE_SIZE
|
||||
#ifdef ALTERA_S10
|
||||
#define L2_CACHE_SIZE 2097152
|
||||
#else
|
||||
#define L2_CACHE_SIZE 1048576
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Number of Banks
|
||||
#ifndef L2_NUM_BANKS
|
||||
#define L2_NUM_BANKS MIN(4, NUM_SOCKETS)
|
||||
#endif
|
||||
|
||||
// Core Response Queue Size
|
||||
#ifndef L2_CRSQ_SIZE
|
||||
#define L2_CRSQ_SIZE 2
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef L2_MSHR_SIZE
|
||||
#define L2_MSHR_SIZE 16
|
||||
#endif
|
||||
|
||||
// Memory Request Queue Size
|
||||
#ifndef L2_MREQ_SIZE
|
||||
#define L2_MREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Memory Response Queue Size
|
||||
#ifndef L2_MRSQ_SIZE
|
||||
#define L2_MRSQ_SIZE 0
|
||||
#endif
|
||||
|
||||
// Number of Associative Ways
|
||||
#ifndef L2_NUM_WAYS
|
||||
#define L2_NUM_WAYS 2
|
||||
#endif
|
||||
|
||||
// L3cache Configurable Knobs /////////////////////////////////////////////////
|
||||
|
||||
// Cache Size
|
||||
#ifndef L3_CACHE_SIZE
|
||||
#ifdef ALTERA_S10
|
||||
#define L3_CACHE_SIZE 2097152
|
||||
#else
|
||||
#define L3_CACHE_SIZE 1048576
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Number of Banks
|
||||
#ifndef L3_NUM_BANKS
|
||||
#define L3_NUM_BANKS MIN(4, NUM_CLUSTERS)
|
||||
#endif
|
||||
|
||||
// Core Response Queue Size
|
||||
#ifndef L3_CRSQ_SIZE
|
||||
#define L3_CRSQ_SIZE 2
|
||||
#endif
|
||||
|
||||
// Miss Handling Register Size
|
||||
#ifndef L3_MSHR_SIZE
|
||||
#define L3_MSHR_SIZE 16
|
||||
#endif
|
||||
|
||||
// Memory Request Queue Size
|
||||
#ifndef L3_MREQ_SIZE
|
||||
#define L3_MREQ_SIZE 4
|
||||
#endif
|
||||
|
||||
// Memory Response Queue Size
|
||||
#ifndef L3_MRSQ_SIZE
|
||||
#define L3_MRSQ_SIZE 0
|
||||
#endif
|
||||
|
||||
// Number of Associative Ways
|
||||
#ifndef L3_NUM_WAYS
|
||||
#define L3_NUM_WAYS 4
|
||||
#endif
|
||||
|
||||
// ISA Extensions /////////////////////////////////////////////////////////////
|
||||
|
||||
#ifdef EXT_A_ENABLE
|
||||
#define EXT_A_ENABLED 1
|
||||
#else
|
||||
#define EXT_A_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef EXT_C_ENABLE
|
||||
#define EXT_C_ENABLED 1
|
||||
#else
|
||||
#define EXT_C_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef EXT_D_ENABLE
|
||||
#define EXT_D_ENABLED 1
|
||||
#else
|
||||
#define EXT_D_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef EXT_F_ENABLE
|
||||
#define EXT_F_ENABLED 1
|
||||
#else
|
||||
#define EXT_F_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef EXT_M_ENABLE
|
||||
#define EXT_M_ENABLED 1
|
||||
#else
|
||||
#define EXT_M_ENABLED 0
|
||||
#endif
|
||||
|
||||
#define ISA_STD_A 0
|
||||
#define ISA_STD_C 2
|
||||
#define ISA_STD_D 3
|
||||
#define ISA_STD_E 4
|
||||
#define ISA_STD_F 5
|
||||
#define ISA_STD_H 7
|
||||
#define ISA_STD_I 8
|
||||
#define ISA_STD_N 13
|
||||
#define ISA_STD_Q 16
|
||||
#define ISA_STD_S 18
|
||||
#define ISA_STD_U 20
|
||||
|
||||
#define ISA_EXT_ICACHE 0
|
||||
#define ISA_EXT_DCACHE 1
|
||||
#define ISA_EXT_L2CACHE 2
|
||||
#define ISA_EXT_L3CACHE 3
|
||||
#define ISA_EXT_SMEM 4
|
||||
|
||||
#define MISA_EXT (ICACHE_ENABLED << ISA_EXT_ICACHE) \
|
||||
| (DCACHE_ENABLED << ISA_EXT_DCACHE) \
|
||||
| (L2_ENABLED << ISA_EXT_L2CACHE) \
|
||||
| (L3_ENABLED << ISA_EXT_L3CACHE) \
|
||||
| (SM_ENABLED << ISA_EXT_SMEM)
|
||||
|
||||
#define MISA_STD (EXT_A_ENABLED << 0) /* A - Atomic Instructions extension */ \
|
||||
| (0 << 1) /* B - Tentatively reserved for Bit operations extension */ \
|
||||
| (EXT_C_ENABLED << 2) /* C - Compressed extension */ \
|
||||
| (EXT_D_ENABLED << 3) /* D - Double precsision floating-point extension */ \
|
||||
| (0 << 4) /* E - RV32E base ISA */ \
|
||||
| (EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \
|
||||
| (0 << 6) /* G - Additional standard extensions present */ \
|
||||
| (0 << 7) /* H - Hypervisor mode implemented */ \
|
||||
| (1 << 8) /* I - RV32I/64I/128I base ISA */ \
|
||||
| (0 << 9) /* J - Reserved */ \
|
||||
| (0 << 10) /* K - Reserved */ \
|
||||
| (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \
|
||||
| (EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \
|
||||
| (0 << 13) /* N - User level interrupts supported */ \
|
||||
| (0 << 14) /* O - Reserved */ \
|
||||
| (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \
|
||||
| (0 << 16) /* Q - Quad-precision floating-point extension */ \
|
||||
| (0 << 17) /* R - Reserved */ \
|
||||
| (0 << 18) /* S - Supervisor mode implemented */ \
|
||||
| (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \
|
||||
| (1 << 20) /* U - User mode implemented */ \
|
||||
| (0 << 21) /* V - Tentatively reserved for Vector extension */ \
|
||||
| (0 << 22) /* W - Reserved */ \
|
||||
| (1 << 23) /* X - Non-standard extensions present */ \
|
||||
| (0 << 24) /* Y - Reserved */ \
|
||||
| (0 << 25) /* Z - Reserved */
|
||||
|
||||
// Device identification //////////////////////////////////////////////////////
|
||||
|
||||
#define VENDOR_ID 0
|
||||
#define ARCHITECTURE_ID 0
|
||||
#define IMPLEMENTATION_ID 0
|
||||
|
||||
#endif // VX_CONFIG_VH
|
||||
|
||||
193
lib/include/VX_types.h
Normal file
193
lib/include/VX_types.h
Normal file
@@ -0,0 +1,193 @@
|
||||
// auto-generated by gen_config.py. DO NOT EDIT
|
||||
// Generated at 2024-06-15 00:25:12.935689
|
||||
|
||||
// Translated from ./rtl/VX_types.vh:
|
||||
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef VX_TYPES_VH
|
||||
#define VX_TYPES_VH
|
||||
|
||||
// Device configuration registers
|
||||
|
||||
#define VX_CSR_ADDR_BITS 12
|
||||
#define VX_DCR_ADDR_BITS 12
|
||||
|
||||
#define VX_DCR_BASE_STATE_BEGIN 0x001
|
||||
#define VX_DCR_BASE_STARTUP_ADDR0 0x001
|
||||
#define VX_DCR_BASE_STARTUP_ADDR1 0x002
|
||||
#define VX_DCR_BASE_MPM_CLASS 0x003
|
||||
#define VX_DCR_BASE_STATE_END 0x004
|
||||
|
||||
#define VX_DCR_BASE_STATE(addr) ((addr) - VX_DCR_BASE_STATE_BEGIN)
|
||||
#define VX_DCR_BASE_STATE_COUNT (VX_DCR_BASE_STATE_END-VX_DCR_BASE_STATE_BEGIN)
|
||||
|
||||
// Machine Performance-monitoring counters classes
|
||||
|
||||
#define VX_DCR_MPM_CLASS_NONE 0
|
||||
#define VX_DCR_MPM_CLASS_CORE 1
|
||||
#define VX_DCR_MPM_CLASS_MEM 2
|
||||
|
||||
// User Floating-Point CSRs
|
||||
|
||||
#define VX_CSR_FFLAGS 0x001
|
||||
#define VX_CSR_FRM 0x002
|
||||
#define VX_CSR_FCSR 0x003
|
||||
|
||||
#define VX_CSR_SATP 0x180
|
||||
|
||||
#define VX_CSR_PMPCFG0 0x3A0
|
||||
#define VX_CSR_PMPADDR0 0x3B0
|
||||
|
||||
#define VX_CSR_MSTATUS 0x300
|
||||
#define VX_CSR_MISA 0x301
|
||||
#define VX_CSR_MEDELEG 0x302
|
||||
#define VX_CSR_MIDELEG 0x303
|
||||
#define VX_CSR_MIE 0x304
|
||||
#define VX_CSR_MTVEC 0x305
|
||||
|
||||
#define VX_CSR_MEPC 0x341
|
||||
|
||||
#define VX_CSR_MNSTATUS 0x744
|
||||
|
||||
#define VX_CSR_MPM_BASE 0xB00
|
||||
#define VX_CSR_MPM_BASE_H 0xB80
|
||||
#define VX_CSR_MPM_USER 0xB03
|
||||
#define VX_CSR_MPM_USER_H 0xB83
|
||||
|
||||
// Machine Performance-monitoring core counters
|
||||
// PERF: Standard
|
||||
#define VX_CSR_MCYCLE 0xB00
|
||||
#define VX_CSR_MCYCLE_H 0xB80
|
||||
#define VX_CSR_MPM_RESERVED 0xB01
|
||||
#define VX_CSR_MPM_RESERVED_H 0xB81
|
||||
#define VX_CSR_MINSTRET 0xB02
|
||||
#define VX_CSR_MINSTRET_H 0xB82
|
||||
// PERF: pipeline
|
||||
#define VX_CSR_MPM_SCHED_ID 0xB03
|
||||
#define VX_CSR_MPM_SCHED_ID_H 0xB83
|
||||
#define VX_CSR_MPM_SCHED_ST 0xB04
|
||||
#define VX_CSR_MPM_SCHED_ST_H 0xB84
|
||||
#define VX_CSR_MPM_IBUF_ST 0xB05
|
||||
#define VX_CSR_MPM_IBUF_ST_H 0xB85
|
||||
#define VX_CSR_MPM_SCRB_ST 0xB06
|
||||
#define VX_CSR_MPM_SCRB_ST_H 0xB86
|
||||
#define VX_CSR_MPM_SCRB_ALU 0xB07
|
||||
#define VX_CSR_MPM_SCRB_ALU_H 0xB87
|
||||
#define VX_CSR_MPM_SCRB_FPU 0xB08
|
||||
#define VX_CSR_MPM_SCRB_FPU_H 0xB88
|
||||
#define VX_CSR_MPM_SCRB_LSU 0xB09
|
||||
#define VX_CSR_MPM_SCRB_LSU_H 0xB89
|
||||
#define VX_CSR_MPM_SCRB_SFU 0xB0A
|
||||
#define VX_CSR_MPM_SCRB_SFU_H 0xB8A
|
||||
// PERF: memory
|
||||
#define VX_CSR_MPM_IFETCHES 0xB0B
|
||||
#define VX_CSR_MPM_IFETCHES_H 0xB8B
|
||||
#define VX_CSR_MPM_LOADS 0xB0C
|
||||
#define VX_CSR_MPM_LOADS_H 0xB8C
|
||||
#define VX_CSR_MPM_STORES 0xB0D
|
||||
#define VX_CSR_MPM_STORES_H 0xB8D
|
||||
#define VX_CSR_MPM_IFETCH_LT 0xB0E
|
||||
#define VX_CSR_MPM_IFETCH_LT_H 0xB8E
|
||||
#define VX_CSR_MPM_LOAD_LT 0xB0F
|
||||
#define VX_CSR_MPM_LOAD_LT_H 0xB8F
|
||||
// SFU: scoreboard
|
||||
#define VX_CSR_MPM_SCRB_WCTL 0xB10
|
||||
#define VX_CSR_MPM_SCRB_WCTL_H 0xB90
|
||||
#define VX_CSR_MPM_SCRB_CSRS 0xB11
|
||||
#define VX_CSR_MPM_SCRB_CSRS_H 0xB91
|
||||
|
||||
// Machine Performance-monitoring memory counters
|
||||
// PERF: icache
|
||||
#define VX_CSR_MPM_ICACHE_READS 0xB03 // total reads
|
||||
#define VX_CSR_MPM_ICACHE_READS_H 0xB83
|
||||
#define VX_CSR_MPM_ICACHE_MISS_R 0xB04 // read misses
|
||||
#define VX_CSR_MPM_ICACHE_MISS_R_H 0xB84
|
||||
#define VX_CSR_MPM_ICACHE_MSHR_ST 0xB05 // MSHR stalls
|
||||
#define VX_CSR_MPM_ICACHE_MSHR_ST_H 0xB85
|
||||
// PERF: dcache
|
||||
#define VX_CSR_MPM_DCACHE_READS 0xB06 // total reads
|
||||
#define VX_CSR_MPM_DCACHE_READS_H 0xB86
|
||||
#define VX_CSR_MPM_DCACHE_WRITES 0xB07 // total writes
|
||||
#define VX_CSR_MPM_DCACHE_WRITES_H 0xB87
|
||||
#define VX_CSR_MPM_DCACHE_MISS_R 0xB08 // read misses
|
||||
#define VX_CSR_MPM_DCACHE_MISS_R_H 0xB88
|
||||
#define VX_CSR_MPM_DCACHE_MISS_W 0xB09 // write misses
|
||||
#define VX_CSR_MPM_DCACHE_MISS_W_H 0xB89
|
||||
#define VX_CSR_MPM_DCACHE_BANK_ST 0xB0A // bank conflicts
|
||||
#define VX_CSR_MPM_DCACHE_BANK_ST_H 0xB8A
|
||||
#define VX_CSR_MPM_DCACHE_MSHR_ST 0xB0B // MSHR stalls
|
||||
#define VX_CSR_MPM_DCACHE_MSHR_ST_H 0xB8B
|
||||
// PERF: l2cache
|
||||
#define VX_CSR_MPM_L2CACHE_READS 0xB0C // total reads
|
||||
#define VX_CSR_MPM_L2CACHE_READS_H 0xB8C
|
||||
#define VX_CSR_MPM_L2CACHE_WRITES 0xB0D // total writes
|
||||
#define VX_CSR_MPM_L2CACHE_WRITES_H 0xB8D
|
||||
#define VX_CSR_MPM_L2CACHE_MISS_R 0xB0E // read misses
|
||||
#define VX_CSR_MPM_L2CACHE_MISS_R_H 0xB8E
|
||||
#define VX_CSR_MPM_L2CACHE_MISS_W 0xB0F // write misses
|
||||
#define VX_CSR_MPM_L2CACHE_MISS_W_H 0xB8F
|
||||
#define VX_CSR_MPM_L2CACHE_BANK_ST 0xB10 // bank conflicts
|
||||
#define VX_CSR_MPM_L2CACHE_BANK_ST_H 0xB90
|
||||
#define VX_CSR_MPM_L2CACHE_MSHR_ST 0xB11 // MSHR stalls
|
||||
#define VX_CSR_MPM_L2CACHE_MSHR_ST_H 0xB91
|
||||
// PERF: l3cache
|
||||
#define VX_CSR_MPM_L3CACHE_READS 0xB12 // total reads
|
||||
#define VX_CSR_MPM_L3CACHE_READS_H 0xB92
|
||||
#define VX_CSR_MPM_L3CACHE_WRITES 0xB13 // total writes
|
||||
#define VX_CSR_MPM_L3CACHE_WRITES_H 0xB93
|
||||
#define VX_CSR_MPM_L3CACHE_MISS_R 0xB14 // read misses
|
||||
#define VX_CSR_MPM_L3CACHE_MISS_R_H 0xB94
|
||||
#define VX_CSR_MPM_L3CACHE_MISS_W 0xB15 // write misses
|
||||
#define VX_CSR_MPM_L3CACHE_MISS_W_H 0xB95
|
||||
#define VX_CSR_MPM_L3CACHE_BANK_ST 0xB16 // bank conflicts
|
||||
#define VX_CSR_MPM_L3CACHE_BANK_ST_H 0xB96
|
||||
#define VX_CSR_MPM_L3CACHE_MSHR_ST 0xB17 // MSHR stalls
|
||||
#define VX_CSR_MPM_L3CACHE_MSHR_ST_H 0xB97
|
||||
// PERF: memory
|
||||
#define VX_CSR_MPM_MEM_READS 0xB18 // total reads
|
||||
#define VX_CSR_MPM_MEM_READS_H 0xB98
|
||||
#define VX_CSR_MPM_MEM_WRITES 0xB19 // total writes
|
||||
#define VX_CSR_MPM_MEM_WRITES_H 0xB99
|
||||
#define VX_CSR_MPM_MEM_LT 0xB1A // memory latency
|
||||
#define VX_CSR_MPM_MEM_LT_H 0xB9A
|
||||
// PERF: smem
|
||||
#define VX_CSR_MPM_SMEM_READS 0xB1B // memory reads
|
||||
#define VX_CSR_MPM_SMEM_READS_H 0xB9B
|
||||
#define VX_CSR_MPM_SMEM_WRITES 0xB1C // memory writes
|
||||
#define VX_CSR_MPM_SMEM_WRITES_H 0xB9C
|
||||
#define VX_CSR_MPM_SMEM_BANK_ST 0xB1D // bank conflicts
|
||||
#define VX_CSR_MPM_SMEM_BANK_ST_H 0xB9D
|
||||
|
||||
// Machine Information Registers
|
||||
|
||||
#define VX_CSR_MVENDORID 0xF11
|
||||
#define VX_CSR_MARCHID 0xF12
|
||||
#define VX_CSR_MIMPID 0xF13
|
||||
#define VX_CSR_MHARTID 0xF14
|
||||
|
||||
// GPGU CSRs
|
||||
|
||||
#define VX_CSR_THREAD_ID 0xCC0
|
||||
#define VX_CSR_WARP_ID 0xCC1
|
||||
#define VX_CSR_CORE_ID 0xCC2
|
||||
#define VX_CSR_WARP_MASK 0xCC3
|
||||
#define VX_CSR_THREAD_MASK 0xCC4 // warning! this value is also used in LLVM
|
||||
|
||||
#define VX_CSR_NUM_THREADS 0xFC0
|
||||
#define VX_CSR_NUM_WARPS 0xFC1
|
||||
#define VX_CSR_NUM_CORES 0xFC2
|
||||
|
||||
#endif // VX_TYPES_VH
|
||||
|
||||
258
lib/include/gemmini_mmio.h
Normal file
258
lib/include/gemmini_mmio.h
Normal file
@@ -0,0 +1,258 @@
|
||||
#ifndef GEMMINI_MMIO_H
|
||||
#define GEMMINI_MMIO_H
|
||||
#ifndef GEMMINI_PARAMS_H
|
||||
#error INCLUDE GEMMINI.H FIRST
|
||||
#endif
|
||||
|
||||
/* shared memory constants and helpers */
|
||||
/* =================================== */
|
||||
#define SMEM_BASE 0xff000000
|
||||
// 16KB
|
||||
// #define SMEM_SIZE 0x4000
|
||||
// 64KB
|
||||
// #define SMEM_SIZE 0x10000
|
||||
// 128KB (FP16 GEMM)
|
||||
#define SMEM_SIZE 0x20000
|
||||
// 256KB (FlashAttention)
|
||||
// #define SMEM_SIZE 0x40000
|
||||
|
||||
#define SMEM_MASK (SMEM_SIZE - 1)
|
||||
#define SMEM_ADDR_END (SMEM_BASE + SMEM_SIZE)
|
||||
|
||||
#define SPAD_BASE 0x0
|
||||
#define SPAD_ROW_SIZE (DIM * sizeof(elem_t))
|
||||
#define SPAD_NUM_ROWS (SMEM_SIZE / SPAD_ROW_SIZE)
|
||||
#define SPAD_MASK (SPAD_NUM_ROWS - 1)
|
||||
|
||||
#define PRINT_BUF ((char *) (SMEM_ADDR_END))
|
||||
#define HW_TID() ({uint32_t gtid; asm volatile ("csrr %0, mhartid" : "=r" (gtid)); gtid;})
|
||||
#define SMEM_TO_SPAD(smem_addr) (SPAD_BASE + ((smem_addr) & SMEM_MASK) / SPAD_ROW_SIZE)
|
||||
#define SPAD_TO_SMEM(spad_addr) (SMEM_BASE + ((spad_addr) & SPAD_MASK) * SPAD_ROW_SIZE)
|
||||
|
||||
// convert normal matrix i,j into tiled smem offset
|
||||
// top_in_tiles = i / DIM
|
||||
// left_in_tiles = j / DIM
|
||||
// num_tiles_before_current = top_in_tiles * (J / DIM) + left_in_tiles
|
||||
// smem_addr = num_tiles_before_current * DIM * DIM + (i % DIM) * DIM + (j % DIM)
|
||||
#define SMEM_MAT_OFFSET(i, j, J) \
|
||||
(((i) / DIM * (J) / DIM + (j) / DIM) * DIM * DIM + ((i) % DIM) * DIM + ((j) % DIM))
|
||||
|
||||
/* gemmini mmio interface */
|
||||
/* ====================== */
|
||||
static size_t gemmini_tile_idx[NUM_THREADS * NUM_WARPS * NUM_CORES * NUM_CLUSTERS] = {0};
|
||||
#define use_gemmini(i) {gemmini_tile_idx[HW_TID()] = (i);}
|
||||
#define GEMMINI_TILE_IDX() (gemmini_tile_idx[HW_TID()])
|
||||
#define GEMMINI_CISC_IMM(x, i) ((x) + 32 * (i))
|
||||
#define GEMMINI_CTRL (SMEM_BASE + SMEM_SIZE + 0x3000 + 0x100 * GEMMINI_TILE_IDX())
|
||||
#define GEMMINI_RS1_ADDR (GEMMINI_CTRL + 0x10)
|
||||
#define GEMMINI_RS2_ADDR (GEMMINI_CTRL + 0x18)
|
||||
#define GEMMINI_INST_ADDR (GEMMINI_CTRL + 0x0)
|
||||
#define GEMMINI_BUSY_ADDR (GEMMINI_CTRL + 0x20)
|
||||
#define GEMMINI_OCCUPANCY_ADDR (GEMMINI_CTRL + 0x28)
|
||||
#undef ROCC_INSTRUCTION_RS1_RS2
|
||||
#define ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) { \
|
||||
*((volatile uint64_t *) GEMMINI_RS1_ADDR) = (rs1); \
|
||||
*((volatile uint64_t *) GEMMINI_RS2_ADDR) = (rs2); \
|
||||
*((volatile uint32_t*) GEMMINI_INST_ADDR) = (0x7B) | (0 << 7) | (3 << 12) | (1 << 15) | (2 << 20) | ((funct) << 25); \
|
||||
}
|
||||
|
||||
/* additional intrinsics */
|
||||
/* ===================== */
|
||||
#define loop_matmul_skips(skip_lda, skip_ldb, skip_ldd, skip_ex, skip_stc) \
|
||||
(((skip_lda) | ((skip_ldb) << 1) | ((skip_ldd) << 2) | ((skip_ex) << 3) | ((skip_stc) << 4)) << 3)
|
||||
|
||||
#define sp_tiled_matmul_full_spad_ws(A_sp_addr_start, B_sp_addr_start, D_sp_addr_start, C_dst_sp_addr_start,\
|
||||
I, J, K, pad_I, pad_J, pad_K, a_transpose, b_transpose, full_C, low_D, acc, act, skips) \
|
||||
gemmini_loop_ws_spad(I, J, K, pad_I, pad_J, pad_K, A_sp_addr_start, (B_sp_addr_start) + (K) * (J) * DIM, NULL, \
|
||||
C_dst_sp_addr_start, a_transpose, b_transpose, full_C, low_D, acc, act, 0, 0, false, skips)
|
||||
|
||||
#define gemmini_status() ({uint32_t status; asm volatile ("csrr %0, 0xacc" : "=r" (status)); status;})
|
||||
|
||||
#undef gemmini_fence
|
||||
//#define gemmini_fence() { while (gemmini_status()); }
|
||||
#define gemmini_fence() { while (*((volatile uint32_t *) GEMMINI_BUSY_ADDR)) asm volatile ("nop"); }
|
||||
|
||||
#define virgo_fence(n) { while (*((volatile uint32_t *) GEMMINI_OCCUPANCY_ADDR) > n) asm volatile ("nop"); }
|
||||
|
||||
/* cisc instructions */
|
||||
/* ================= */
|
||||
|
||||
// bits [4:0] is the opcode
|
||||
// bits [7:5] is the target gemmini id, zero-indexed
|
||||
// #define GEMMINI_CISC_CMD_I(x) asm("csrwi 0xacc, %0" :: "i" (x))
|
||||
#define GEMMINI_CISC_CMD_I(x) asm("csrw 0xacc, %0" :: "r" (x)) // use registers even for immediate calls for now
|
||||
#define GEMMINI_CISC_CMD_R(x) asm("csrw 0xacc, %0" :: "r" (x))
|
||||
|
||||
#define GEMMINI_CISC_COMPUTE_HEXADECILES 0
|
||||
#define GEMMINI_CISC_COMPUTE_AND_STORE_TO_SPAD 1
|
||||
#define GEMMINI_CISC_MANUAL 2
|
||||
#define GEMMINI_CISC_SET_AB_STRIDE 8
|
||||
#define GEMMINI_CISC_STORE_TO_SPAD 9
|
||||
#define GEMMINI_CISC_LOAD_TO_HEXADECILES 10
|
||||
#define GEMMINI_CISC_SET_DC_STRIDE 11
|
||||
#define GEMMINI_CISC_STORE_TO_GMEM 12
|
||||
|
||||
/* high level virgo routines */
|
||||
/* ========================= */
|
||||
inline void gemmini_tile_load_ab(const elem_t * const a_addr, const elem_t * const b_addr,
|
||||
const uint32_t a_hexadecile, const uint32_t b_hexadecile,
|
||||
const uint32_t tile_idx_i, const uint32_t tile_idx_j, const uint32_t tile_idx_k,
|
||||
const uint32_t mat_size_m, const uint32_t mat_size_n, const uint32_t mat_size_k,
|
||||
const uint32_t tile_size_m, const uint32_t tile_size_n, const uint32_t tile_size_k) {
|
||||
|
||||
ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC,
|
||||
(uint64_t) (a_addr + tile_idx_i * tile_size_m * mat_size_k + tile_idx_k * tile_size_k),
|
||||
(uint64_t) (b_addr + tile_idx_k * tile_size_k * mat_size_n + tile_idx_j * tile_size_n), k_LOOP_WS_CONFIG_ADDRS_AB)
|
||||
GEMMINI_CISC_CMD_R((mat_size_n << 20) | (mat_size_k << 8) | GEMMINI_CISC_SET_AB_STRIDE);
|
||||
GEMMINI_CISC_CMD_R((b_hexadecile << 16) | (a_hexadecile << 8) | GEMMINI_CISC_LOAD_TO_HEXADECILES);
|
||||
}
|
||||
|
||||
template <bool store_to_spad = false>
|
||||
inline void gemmini_tile_compute(const uint32_t a_hexadecile,
|
||||
const uint32_t b_hexadecile,
|
||||
const uint32_t d_hexadecile,
|
||||
const bool accumulate) {
|
||||
if constexpr (!store_to_spad) {
|
||||
GEMMINI_CISC_CMD_R((static_cast<uint32_t>(accumulate) << 24) |
|
||||
(b_hexadecile << 16) | (a_hexadecile << 8) |
|
||||
GEMMINI_CISC_COMPUTE_HEXADECILES);
|
||||
} else {
|
||||
GEMMINI_CISC_CMD_R((d_hexadecile << 24) | (b_hexadecile << 16) |
|
||||
(a_hexadecile << 8) | GEMMINI_CISC_COMPUTE_AND_STORE_TO_SPAD);
|
||||
}
|
||||
}
|
||||
|
||||
inline void gemmini_tile_store_c_gmem(elem_t * const c_addr,
|
||||
const uint32_t tile_idx_i, const uint32_t tile_idx_j,
|
||||
const uint32_t mat_size_m, const uint32_t mat_size_n,
|
||||
const uint32_t tile_size_m, const uint32_t tile_size_n) {
|
||||
|
||||
elem_t * const dram_c_tile_start = c_addr + tile_idx_i * tile_size_m * mat_size_n + tile_idx_j * tile_size_n;
|
||||
ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, (uint64_t) dram_c_tile_start, k_LOOP_WS_CONFIG_ADDRS_DC)
|
||||
|
||||
GEMMINI_CISC_CMD_R((mat_size_n << 20) | GEMMINI_CISC_SET_DC_STRIDE);
|
||||
GEMMINI_CISC_CMD_I(GEMMINI_CISC_STORE_TO_GMEM);
|
||||
|
||||
// ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, BOUND_INST, k_LOOP_WS_CONFIG_BOUNDS)
|
||||
// ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, mat_size_n, k_LOOP_WS_CONFIG_STRIDES_DC)
|
||||
// ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, 0, loop_matmul_skips(1, 1, 1, 1, 0), k_LOOP_WS)
|
||||
}
|
||||
|
||||
inline void gemmini_tile_store_c_spad(const uint32_t c_hexadecile) {
|
||||
GEMMINI_CISC_CMD_R(((uint32_t) (c_hexadecile << 8)) | GEMMINI_CISC_STORE_TO_SPAD);
|
||||
}
|
||||
|
||||
inline void gemmini_manual_job() {
|
||||
GEMMINI_CISC_CMD_I(GEMMINI_CISC_MANUAL);
|
||||
}
|
||||
|
||||
/* inline static void sp_tiled_matmul_full_spad_ws(const uint32_t A_sp_addr_start, const uint32_t B_sp_addr_start,
|
||||
const uint32_t D_sp_addr_start, const uint32_t C_dst_sp_addr_start,
|
||||
size_t I, size_t J, size_t K, size_t pad_I, size_t pad_J, size_t pad_K,
|
||||
bool a_transpose, bool b_transpose,
|
||||
bool full_C, bool low_D, bool acc,
|
||||
int act, int skip_mvout) {
|
||||
|
||||
gemmini_loop_ws_spad(I, J, K, pad_I, pad_J, pad_K,
|
||||
A_sp_addr_start, B_sp_addr_start + K * J * DIM, NULL, C_dst_sp_addr_start,
|
||||
a_transpose, b_transpose,
|
||||
full_C, low_D, acc,
|
||||
act, 0, 0, false, skip_mvout); */
|
||||
/*
|
||||
return;
|
||||
|
||||
|
||||
// const uint32_t A_sp_addr_start = 0;
|
||||
// const uint32_t B_sp_addr_start = BANK_NUM * BANK_ROWS - K * J * DIM;
|
||||
// const uint32_t D_sp_addr_start = 1 << (ADDR_LEN-1);
|
||||
const uint32_t C_sp_addr_start = 2 << (ADDR_LEN-2) | (full_C << (ADDR_LEN-3));
|
||||
// const int D_blocks = low_D ? (J <= MAX_BLOCK_LEN ? J : MAX_BLOCK_LEN) :
|
||||
// (J <= MAX_BLOCK_LEN_ACC ? J : MAX_BLOCK_LEN_ACC);
|
||||
const int C_blocks = 1; //full_C ? 1 : (J <= MAX_BLOCK_LEN ? J : MAX_BLOCK_LEN);
|
||||
// const size_t sizeof_D = low_D ? sizeof(elem_t) : sizeof(acc_t);
|
||||
const size_t sizeof_C = full_C ? sizeof(acc_t) : sizeof(elem_t);
|
||||
gemmini_fence();
|
||||
|
||||
if (a_transpose || b_transpose || (I < 4)) {
|
||||
for (size_t k = 0; k < K; k++) {
|
||||
for (size_t j = 0; j < J; j++) {
|
||||
for (size_t i = 0; i < I; i++) {
|
||||
const uint32_t A_sp_addr = a_transpose ? (A_sp_addr_start + (k*I + i)*DIM) :
|
||||
(A_sp_addr_start + (i*K + k)*DIM);
|
||||
const uint32_t B_sp_addr = b_transpose ? (B_sp_addr_start + (j*K + k)*DIM) :
|
||||
(B_sp_addr_start + (k*J + j)*DIM);
|
||||
const uint32_t C_sp_addr = C_sp_addr_start + (i*J + j)*DIM;
|
||||
// Compute
|
||||
uint32_t pre_sp_addr = i == 0 ? B_sp_addr : GARBAGE_ADDR;
|
||||
uint32_t out_sp_addr = C_sp_addr | ((k == 0 ? 0 : 1) << (ADDR_LEN-2));
|
||||
gemmini_extended_preload(pre_sp_addr, out_sp_addr, DIM, DIM, DIM, DIM);
|
||||
if (i == 0) { // First iteration
|
||||
gemmini_extended_compute_preloaded(A_sp_addr, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
} else { // All other iterations
|
||||
gemmini_extended_compute_accumulated(A_sp_addr, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
}
|
||||
if (k == K - 1) {
|
||||
// Move-out C (if not normalizing)
|
||||
// if (((act != LAYERNORM) && (act != SOFTMAX)) && (j == J-1 || j % C_blocks == C_blocks-1)) {
|
||||
const size_t rounded_j = j; // (j / C_blocks) * C_blocks;
|
||||
const uint32_t rounded_C_sp_addr = C_sp_addr; // C_sp_addr_start + (i*J + rounded_j)*DIM;
|
||||
|
||||
const uint32_t C_dst_sp_addr = ((uint32_t) C_dst_sp_addr_start) + (i * J + rounded_j) * DIM; // * DIM * sizeof_C;
|
||||
|
||||
// const size_t blocks = rounded_j + C_blocks <= J ? C_blocks : J-rounded_j;
|
||||
constexpr size_t cols = DIM; // blocks * DIM - (rounded_j + blocks >= J ? pad_J : 0);
|
||||
constexpr size_t rows = DIM; // DIM - (i == I - 1 ? pad_I : 0);
|
||||
|
||||
gemmini_extended_mvout_spad(C_dst_sp_addr, 1, rounded_C_sp_addr, cols, rows);
|
||||
// }
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (size_t k = 0; k < K; k++) {
|
||||
for (size_t j = 0; j < J; j++) {
|
||||
uint32_t A_sp_addr = A_sp_addr_start + k * DIM; // (i*K + k)*DIM;
|
||||
const uint32_t B_sp_addr = B_sp_addr_start + (k*J + j)*DIM;
|
||||
uint32_t C_sp_addr = C_sp_addr_start + j * DIM; // (i*J + j)*DIM;
|
||||
for (size_t i = 0; i < I; i += 4) {
|
||||
// Compute
|
||||
// constexpr uint32_t pre_sp_addr = i == 0 ? B_sp_addr : GARBAGE_ADDR;
|
||||
const uint32_t out_sp_addr = C_sp_addr | ((k == 0 ? 0 : 1) << (ADDR_LEN-2));
|
||||
if (i == 0) { // First iteration
|
||||
gemmini_extended_preload(B_sp_addr, out_sp_addr, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_preloaded(A_sp_addr, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + 2 * J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + 2 * K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + 3 * J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + 3 * K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
} else { // All other iterations
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + 2 * J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + 2 * K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_preload(GARBAGE_ADDR, out_sp_addr + 3 * J * DIM, DIM, DIM, DIM, DIM);
|
||||
gemmini_extended_compute_accumulated(A_sp_addr + 3 * K * DIM, GARBAGE_ADDR, DIM, DIM, DIM, DIM);
|
||||
}
|
||||
if (k == K - 1) {
|
||||
for (int x = 0; x < 3; x++) gemmini_fence();
|
||||
gemmini_extended_mvout_spad((uint32_t) C_dst_sp_addr_start + (i * J + j) * DIM, 1, C_sp_addr, DIM, DIM);
|
||||
gemmini_extended_mvout_spad((uint32_t) C_dst_sp_addr_start + ((i + 1) * J + j) * DIM, 1, C_sp_addr + J * DIM, DIM, DIM);
|
||||
gemmini_extended_mvout_spad((uint32_t) C_dst_sp_addr_start + ((i + 2) * J + j) * DIM, 1, C_sp_addr + 2 * J * DIM, DIM, DIM);
|
||||
gemmini_extended_mvout_spad((uint32_t) C_dst_sp_addr_start + ((i + 3) * J + j) * DIM, 1, C_sp_addr + 3 * J * DIM, DIM, DIM);
|
||||
}
|
||||
A_sp_addr += 4 * K * DIM;
|
||||
C_sp_addr += 4 * J * DIM;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
gemmini_fence();
|
||||
}*/
|
||||
|
||||
|
||||
#endif
|
||||
228
lib/include/vx_intrinsics.h
Normal file
228
lib/include/vx_intrinsics.h
Normal file
@@ -0,0 +1,228 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef __VX_INTRINSICS_H__
|
||||
#define __VX_INTRINSICS_H__
|
||||
|
||||
#include <VX_config.h>
|
||||
#include <VX_types.h>
|
||||
|
||||
#if defined(__clang__)
|
||||
#define __UNIFORM__ __attribute__((annotate("vortex.uniform")))
|
||||
#else
|
||||
#define __UNIFORM__
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define __ASM_STR(x) x
|
||||
#else
|
||||
#define __ASM_STR(x) #x
|
||||
#endif
|
||||
|
||||
#define RISCV_CUSTOM0 0x0B
|
||||
#define RISCV_CUSTOM1 0x2B
|
||||
#define RISCV_CUSTOM2 0x5B
|
||||
#define RISCV_CUSTOM3 0x7B
|
||||
|
||||
#define csr_read(csr) ({ \
|
||||
unsigned __r; \
|
||||
__asm__ __volatile__ ("csrr %0, %1" : "=r" (__r) : "i" (csr)); \
|
||||
__r; \
|
||||
})
|
||||
|
||||
#define csr_write(csr, val) ({ \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "r" (__v)); \
|
||||
})
|
||||
|
||||
#define csr_swap(csr, val) ({ \
|
||||
unsigned __r; \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
|
||||
__r; \
|
||||
})
|
||||
|
||||
#define csr_read_set(csr, val) ({ \
|
||||
unsigned __r; \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
|
||||
__r; \
|
||||
})
|
||||
|
||||
#define csr_set(csr, val) ({ \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "r" (__v)); \
|
||||
})
|
||||
|
||||
#define csr_read_clear(csr, val) ({ \
|
||||
unsigned __r; \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
|
||||
__r; \
|
||||
})
|
||||
|
||||
#define csr_clear(csr, val) ({ \
|
||||
unsigned __v = (unsigned)(val); \
|
||||
if (__builtin_constant_p(val) && __v < 32) \
|
||||
__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "i" (__v)); \
|
||||
else \
|
||||
__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "r" (__v)); \
|
||||
})
|
||||
|
||||
// Conditional move
|
||||
inline unsigned vx_cmov(unsigned c, unsigned t, unsigned f) {
|
||||
unsigned ret;
|
||||
asm volatile (".insn r4 %1, 1, 0, %0, %2, %3, %4" : "=r"(ret) : "i"(RISCV_CUSTOM1), "r"(c), "r"(t), "r"(f));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Set thread mask
|
||||
inline void vx_tmc(unsigned thread_mask) {
|
||||
asm volatile (".insn r %0, 0, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(thread_mask));
|
||||
}
|
||||
|
||||
// disable all threads in the current warp
|
||||
inline void vx_tmc_zero() {
|
||||
asm volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM0));
|
||||
}
|
||||
|
||||
// switch execution to single thread zero
|
||||
inline void vx_tmc_one() {
|
||||
asm volatile (
|
||||
"li a0, 1\n\t" // Load immediate value 1 into a0 (x10) register
|
||||
".insn r %0, 0, 0, x0, a0, x0" :: "i"(RISCV_CUSTOM0)
|
||||
: "a0" // Indicate that a0 (x10) is clobbered
|
||||
);
|
||||
}
|
||||
|
||||
// Set thread predicate
|
||||
inline void vx_pred(unsigned condition, unsigned thread_mask) {
|
||||
asm volatile (".insn r %0, 5, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(condition), "r"(thread_mask));
|
||||
}
|
||||
|
||||
typedef void (*vx_wspawn_pfn)();
|
||||
|
||||
// Spawn warps
|
||||
inline void vx_wspawn(unsigned num_warps, vx_wspawn_pfn func_ptr) {
|
||||
asm volatile (".insn r %0, 1, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(num_warps), "r"(func_ptr));
|
||||
}
|
||||
|
||||
// Split on a predicate
|
||||
inline unsigned vx_split(unsigned predicate) {
|
||||
unsigned ret;
|
||||
asm volatile (".insn r %1, 2, 0, %0, %2, x0" : "=r"(ret) : "i"(RISCV_CUSTOM0), "r"(predicate));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Join
|
||||
inline void vx_join(unsigned stack_ptr) {
|
||||
asm volatile (".insn r %0, 3, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(stack_ptr));
|
||||
}
|
||||
|
||||
// Warp Barrier
|
||||
__attribute__((convergent))
|
||||
inline void vx_barrier(unsigned barried_id, unsigned num_warps) {
|
||||
asm volatile (".insn r %0, 4, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(barried_id), "r"(num_warps));
|
||||
}
|
||||
|
||||
// Return current thread identifier
|
||||
inline int vx_thread_id() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_ID));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return current warp identifier
|
||||
inline int vx_warp_id() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_ID));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return current core identifier
|
||||
inline int vx_core_id() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_CORE_ID));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return current thread mask
|
||||
inline int vx_thread_mask() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_MASK));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return number of active warps
|
||||
inline int vx_active_warps() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_MASK));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return the number of threads per warp
|
||||
inline int vx_num_threads() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_THREADS));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return the number of warps per core
|
||||
inline int vx_num_warps() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_WARPS));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return the number of cores per cluster
|
||||
inline int vx_num_cores() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_CORES));
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Return the hart identifier (thread id accross the processor)
|
||||
inline int vx_hart_id() {
|
||||
int ret;
|
||||
asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_MHARTID));
|
||||
return ret;
|
||||
}
|
||||
|
||||
inline void vx_fence() {
|
||||
asm volatile ("fence iorw, iorw");
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __VX_INTRINSICS_H__
|
||||
34
lib/include/vx_print.h
Normal file
34
lib/include/vx_print.h
Normal file
@@ -0,0 +1,34 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef __VX_PRINT_H__
|
||||
#define __VX_PRINT_H__
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int vx_vprintf(const char* format, va_list va);
|
||||
int vx_printf(const char * format, ...);
|
||||
|
||||
void vx_putchar(int c);
|
||||
void vx_putint(int value, int base);
|
||||
void vx_putfloat(float value, int precision);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __VX_PRINT_H__
|
||||
64
lib/include/vx_spawn.h
Normal file
64
lib/include/vx_spawn.h
Normal file
@@ -0,0 +1,64 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef __VX_SPAWN_H__
|
||||
#define __VX_SPAWN_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#ifndef CORES_PER_CLUSTER
|
||||
#define CORES_PER_CLUSTER 8
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t num_groups[3];
|
||||
uint32_t global_offset[3];
|
||||
uint32_t local_size[3];
|
||||
char * printf_buffer;
|
||||
uint32_t *printf_buffer_position;
|
||||
uint32_t printf_buffer_capacity;
|
||||
uint32_t work_dim;
|
||||
} context_t;
|
||||
|
||||
typedef void (*vx_spawn_kernel_cb) (
|
||||
const void * /* arg */,
|
||||
const context_t * /* context */,
|
||||
uint32_t /* group_x */,
|
||||
uint32_t /* group_y */,
|
||||
uint32_t /* group_z */
|
||||
);
|
||||
|
||||
typedef void (*vx_spawn_tasks_cb)(int task_id, void *arg);
|
||||
|
||||
typedef void (*vx_serial_cb)(void *arg);
|
||||
|
||||
void vx_wspawn_wait();
|
||||
|
||||
void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg);
|
||||
|
||||
void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback, void * arg);
|
||||
void vx_spawn_tasks_cluster(int num_tasks, vx_spawn_tasks_cb callback, void * arg);
|
||||
void vx_spawn_tasks_contiguous(int num_tasks, vx_spawn_tasks_cb callback , void * arg);
|
||||
|
||||
void vx_serial(vx_serial_cb callback, void * arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __VX_SPAWN_H__
|
||||
Reference in New Issue
Block a user