wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ibuffer addition

Browse Source
This commit is contained in:
Blaise Tine
2020-08-22 00:22:04 -07:00
parent 6c12391338
commit 0b355f228e
80 changed files with 1811 additions and 1528 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
hw/rtl/libs/VX_cam_buffer.v
View File

@@ -1,19 +1,21 @@
`include "VX_platform.vh"
module VX_cam_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter RPORTS = 1,
parameter DATAW = 1,
parameter SIZE = 1,
parameter RPORTS = 1,
parameter CPORTS = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
input wire [DATAW-1:0] write_data,
output wire [ADDRW-1:0] write_addr,
input wire [DATAW-1:0] write_data,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
input wire [RPORTS-1:0] release_slot,
input wire [CPORTS-1:0][ADDRW-1:0] release_addr,
input wire [CPORTS-1:0] release_slot,
output wire full
);
reg [DATAW-1:0] entries [SIZE-1:0];
@@ -34,12 +36,11 @@ module VX_cam_buffer #(
always @(*) begin
free_slots_n = free_slots;
for (integer i = 0; i < RPORTS; i++) begin
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
free_slots_n[read_addr[i]] = 1;
end
read_data[i] = entries[read_addr[i]];
end
free_slots_n[release_addr[i]] = 1;
end
end
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
@@ -55,15 +56,19 @@ module VX_cam_buffer #(
assert(1 == free_slots[write_addr]) else $display("%t: inused slot at port %d", $time, write_addr);
entries[write_addr] <= write_data;
end
for (integer i = 0; i < RPORTS; i++) begin
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[read_addr[i]]) else $display("%t: freed slot at port %d", $time, read_addr[i]);
assert(0 == free_slots[release_addr[i]]) else $display("%t: freed slot at port %d", $time, release_addr[i]);
end
end
free_slots <= free_slots_n;
write_addr_r <= free_index;
full_r <= ~free_valid;
end
end
for (genvar i = 0; i < RPORTS; i++) begin
assign read_data[i] = entries[read_addr[i]];
end
assign write_addr = write_addr_r;

64
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -14,53 +14,25 @@ module VX_elastic_buffer #(
input wire ready_out,
output wire valid_out
);
if (0 == SIZE) begin
wire empty, full;
reg [DATAW-1:0] skid_buffer;
reg skid_valid;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED)
) queue (
.clk (clk),
.reset (reset),
.push (valid_in),
.pop (ready_out),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
always @(posedge clk) begin
if (reset) begin
skid_valid <= 0;
end else begin
if (valid_in && ~ready_out) begin
assert(~skid_valid);
skid_buffer <= data_in;
skid_valid <= 1;
end
if (ready_out) begin
skid_valid <= 0;
end
end
end
assign ready_in = ready_out || ~skid_valid;
assign data_out = skid_valid ? skid_buffer : data_in;
assign valid_out = valid_in || skid_valid;
end else begin
wire empty, full;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED)
) queue (
.clk (clk),
.reset (reset),
.push (valid_in),
.pop (ready_out),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign ready_in = ~full;
assign valid_out = ~empty;
end
assign ready_in = ~full;
assign valid_out = ~empty;
endmodule

1
hw/rtl/libs/VX_generic_queue.v
View File

@@ -70,7 +70,6 @@ module VX_generic_queue #(
if (writing) begin
data[wr_ptr_a] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
size_r <= size_r + 1;
end

4
hw/rtl/libs/VX_rr_arbiter.v
View File

@@ -36,14 +36,14 @@ module VX_rr_arbiter #(
end
end
grant_onehot_r = N'(0);
grant_onehot_r[grant_index] = 1;
grant_onehot_r[grant_table[state]] = 1;
end
always @(posedge clk) begin
if (reset) begin
state <= 0;
end else begin
state <= grant_index;
state <= grant_table[state];
end
end

65
hw/rtl/libs/VX_skid_buffer.v Normal file
View File

@@ -0,0 +1,65 @@
`include "VX_platform.vh"
module VX_skid_buffer #(
parameter DATAW = 1
) (
input wire clk,
input wire reset,
input wire valid_in,
output reg ready_in,
input wire [DATAW-1:0] data_in,
output reg [DATAW-1:0] data_out,
input wire ready_out,
output reg valid_out
);
reg [DATAW-1:0] buffer;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
use_buffer <= 0;
valid_out <= 0;
end else begin
if (push && (valid_out && !ready_out)) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (ready_out) begin
use_buffer <= 0;
end
if (push) begin
buffer <= data_in;
end
if (!valid_out || ready_out) begin
valid_out <= valid_in || use_buffer;
data_out <= use_buffer ? buffer : data_in;
end
end
end
assign ready_in = !use_buffer;
/*wire empty, full;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (2),
.BUFFERED (0)
) queue (
.clk (clk),
.reset (reset),
.push (valid_in),
.pop (ready_out),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign ready_in = ~full;
assign valid_out = ~empty;*/
endmodule