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This commit is contained in:
Blaise Tine
2020-08-22 00:22:04 -07:00
parent 6c12391338
commit 0b355f228e
80 changed files with 1811 additions and 1528 deletions
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19
hw/rtl/fp_cores/altera/VX_fp_add.v
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@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_add (
module VX_fp_add #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_add (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_add (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_div.v
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@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_div (
module VX_fp_div #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_div (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_div fdiv (
.clk (clk),
.areset (1'b0),
@@ -34,7 +37,7 @@ module VX_fp_div (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FDIV)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
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@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_ftoi (
module VX_fp_ftoi #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_ftoi (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftoi ftoi (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_ftoi (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOI)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_ftou.v
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@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_ftou (
module VX_fp_ftou #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_ftou (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_ftou ftou (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_ftou (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FTOU)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_itof.v
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@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_itof (
module VX_fp_itof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_itof (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_itof itof (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_itof (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_ITOF)
) shift_reg (
.clk(clk),

27
hw/rtl/fp_cores/altera/VX_fp_madd.v
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@@ -1,22 +1,25 @@
`include "VX_define.vh"
module VX_fp_madd (
module VX_fp_madd #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
input wire [`NUM_THREADS-1:0][31:0] datac,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -24,11 +27,11 @@ module VX_fp_madd (
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
@@ -111,7 +114,7 @@ module VX_fp_madd (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1 + 1),
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
@@ -122,7 +125,7 @@ module VX_fp_madd (
);
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),

27
hw/rtl/fp_cores/altera/VX_fp_msub.v
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@@ -1,22 +1,25 @@
`include "VX_define.vh"
module VX_fp_msub (
module VX_fp_msub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
input wire [`NUM_THREADS-1:0][31:0] datac,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
input wire [LANES-1:0][31:0] datac,
output wire [LANES-1:0][31:0] result,
input wire negate,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -24,11 +27,11 @@ module VX_fp_msub (
wire enable0, enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire [LANES-1:0][31:0] result_st0, result_st1;
wire [TAGW-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),
@@ -111,7 +114,7 @@ module VX_fp_msub (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1 + 1),
.DATAW(TAGW + 1 + 1),
.DEPTH(1)
) shift_reg0 (
.clk(clk),
@@ -122,7 +125,7 @@ module VX_fp_msub (
);
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg1 (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_mul.v
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@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_mul (
module VX_fp_mul #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_mul (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_mul (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
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@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_sqrt (
module VX_fp_sqrt #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_sqrt (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_sqrt fsqrt (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_sqrt (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_FSQRT)
) shift_reg (
.clk(clk),

19
hw/rtl/fp_cores/altera/VX_fp_sub.v
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@@ -1,19 +1,22 @@
`include "VX_define.vh"
module VX_fp_sub (
module VX_fp_sub #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
input wire [LANES-1:0][31:0] datab,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -22,7 +25,7 @@ module VX_fp_sub (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),
@@ -65,7 +68,7 @@ module VX_fp_sub (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(1)
) shift_reg (
.clk(clk),

17
hw/rtl/fp_cores/altera/VX_fp_utof.v
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@@ -1,18 +1,21 @@
`include "VX_define.vh"
module VX_fp_utof (
module VX_fp_utof #(
parameter TAGW = 1,
parameter LANES = 1
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [TAGW-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
input wire [LANES-1:0][31:0] dataa,
output wire [LANES-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] tag_out,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
@@ -21,7 +24,7 @@ module VX_fp_utof (
wire enable = ~stall;
assign ready_in = enable;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < LANES; i++) begin
acl_fp_utof utof (
.clk (clk),
.areset (1'b0),
@@ -32,7 +35,7 @@ module VX_fp_utof (
end
VX_shift_register #(
.DATAW(`ISTAG_BITS + 1),
.DATAW(TAGW + 1),
.DEPTH(`LATENCY_UTOF)
) shift_reg (
.clk(clk),