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@@ -3,15 +3,15 @@
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module VX_gpu_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input wire clk,
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input wire reset,
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// Input
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VX_gpu_req_if gpu_req_if,
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VX_gpu_req_if gpu_req_if,
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// Output
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VX_warp_ctl_if warp_ctl_if,
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VX_exu_to_cmt_if gpu_commit_if
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VX_warp_ctl_if warp_ctl_if,
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VX_exu_to_cmt_if gpu_commit_if
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);
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gpu_tmc_t tmc;
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gpu_wspawn_t wspawn;
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@@ -23,15 +23,13 @@ module VX_gpu_unit #(
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wire is_split = (gpu_req_if.op == `GPU_SPLIT);
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wire is_bar = (gpu_req_if.op == `GPU_BAR);
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wire gpu_req_fire = gpu_req_if.valid;
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// tmc
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wire [`NUM_THREADS-1:0] tmc_new_mask;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tmc_new_mask[i] = (i < gpu_req_if.rs1_data[0]);
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end
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assign tmc.valid = gpu_req_fire && is_tmc;
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assign tmc.valid = is_tmc;
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assign tmc.thread_mask = tmc_new_mask;
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// wspawn
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@@ -41,7 +39,7 @@ module VX_gpu_unit #(
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for (genvar i = 0; i < `NUM_WARPS; i++) begin
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assign wspawn_wmask[i] = (i < gpu_req_if.rs1_data[0]);
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end
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assign wspawn.valid = gpu_req_fire && is_wspawn;
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assign wspawn.valid = is_wspawn;
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assign wspawn.wmask = wspawn_wmask;
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assign wspawn.pc = wspawn_pc;
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@@ -56,7 +54,7 @@ module VX_gpu_unit #(
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assign split_else_mask[i] = gpu_req_if.thread_mask[i] & ~taken;
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end
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assign split.valid = gpu_req_fire && is_split;
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assign split.valid = is_split;
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assign split.diverged = (| split_then_mask) && (| split_else_mask);
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assign split.then_mask = split_then_mask;
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assign split.else_mask = split_else_mask;
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@@ -64,23 +62,29 @@ module VX_gpu_unit #(
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// barrier
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assign barrier.valid = is_bar && gpu_req_fire;
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assign barrier.id = gpu_req_if.rs1_data[0][`NB_BITS-1:0];
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assign barrier.num_warps = (`NW_BITS+1)'(gpu_req_if.rs2_data - 1);
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assign barrier.valid = is_bar;
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assign barrier.id = gpu_req_if.rs1_data[0][`NB_BITS-1:0];
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assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data - 1);
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// output
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wire stall = ~gpu_commit_if.ready && gpu_commit_if.valid;
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + $bits(gpu_tmc_t) + $bits(gpu_wspawn_t) + $bits(gpu_split_t) + $bits(gpu_barrier_t))
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.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + $bits(gpu_tmc_t) + $bits(gpu_wspawn_t) + $bits(gpu_split_t) + $bits(gpu_barrier_t))
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) gpu_reg (
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.clk (clk),
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.reset (reset),
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.stall (0),
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.stall (stall),
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.flush (0),
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.in ({gpu_req_if.valid, gpu_req_if.issue_tag, gpu_req_if.wid, tmc, wspawn, split, barrier}),
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.out ({gpu_commit_if.valid, gpu_commit_if.issue_tag, warp_ctl_if.wid, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier})
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.in ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.thread_mask, gpu_req_if.curr_PC, gpu_req_if.rd, gpu_req_if.wb, tmc, wspawn, split, barrier}),
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.out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.thread_mask, gpu_commit_if.curr_PC, gpu_commit_if.rd, gpu_commit_if.wb, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.barrier})
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);
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assign gpu_req_if.ready = 1'b1;
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assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready;
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assign warp_ctl_if.wid = gpu_commit_if.wid;
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// can accept new request?
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assign gpu_req_if.ready = ~stall;
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endmodule
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