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minor update

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Blaise Tine
2020-09-01 00:56:10 -07:00
parent 4e8b9fb296
commit 0a45a8beb3
11 changed files with 34 additions and 21 deletions
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hw/syn/quartus/project.tcl
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@@ -38,6 +38,8 @@ set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NDEBUG
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name VERILOG_MACRO FPU_FAST
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"