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This commit is contained in:
Blaise Tine
2020-06-23 09:28:24 -07:00
parent f80e7c31de
commit 0a01385a2c
24 changed files with 228 additions and 226 deletions
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4
hw/rtl/libs/VX_divide.v
View File

@@ -104,8 +104,8 @@ module VX_divide #(
remainder = 0;
end
else begin
quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end));
quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
end
end
end

14
hw/rtl/libs/VX_generic_queue.v
View File

@@ -60,12 +60,12 @@ module VX_generic_queue #(
if (0 == BUFFERED_OUTPUT) begin
reg [`LOG2UP(SIZE):0] wr_ptr_r;
reg [`LOG2UP(SIZE):0] rd_ptr_r;
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
reg [`LOG2UP(SIZE):0] wr_ptr_r;
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= 0;
@@ -108,12 +108,14 @@ module VX_generic_queue #(
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
head_r <= 0;
curr_r <= 0;
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
empty_r <= 1;
full_r <= 0;
size_r <= 0;
full_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;

4
hw/rtl/libs/VX_generic_register.v
View File

@@ -2,7 +2,7 @@
module VX_generic_register #(
parameter N,
parameter PassThru = 0
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -23,6 +23,6 @@ module VX_generic_register #(
end
end
assign out = PassThru ? in : value;
assign out = PASSTHRU ? in : value;
endmodule

11
hw/rtl/libs/VX_indexable_queue.v
View File

@@ -9,18 +9,18 @@ module VX_indexable_queue #(
input wire [DATAW-1:0] write_data,
output wire [`LOG2UP(SIZE)-1:0] write_addr,
input wire push,
output wire full,
input wire pop,
output wire full,
output wire empty,
input wire [`LOG2UP(SIZE)-1:0] read_addr,
output wire [DATAW-1:0] read_data
);
reg [DATAW-1:0] data [SIZE-1:0];
reg valid [SIZE-1:0];
reg [SIZE-1:0] valid;
reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;
wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;
wire enqueue, dequeue, empty;
wire enqueue, dequeue;
assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];
assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];
@@ -31,10 +31,13 @@ module VX_indexable_queue #(
assign enqueue = push && ~full;
assign dequeue = ~empty && ~valid[rd_a]; // auto-remove when head is invalid
integer i;
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 0;
wr_ptr <= 0;
valid <= 0;
end else begin
if (enqueue) begin
data[wr_a] <= write_data;

2
hw/rtl/libs/VX_mult.v
View File

@@ -107,7 +107,7 @@ module VX_mult #(
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;

29
hw/rtl/libs/VX_scope.v
View File

@@ -58,21 +58,21 @@ module VX_scope #(
always @(posedge clk) begin
if (reset) begin
out_cmd <= $bits(out_cmd)'(CMD_GET_VALID);
raddr <= 0;
waddr <= 0;
waddr_end <= $bits(waddr)'(SIZE-1);
started <= 0;
start_wait <= 0;
recording <= 0;
delay_cntr <= 0;
read_offset <= 0;
data_valid <= 0;
out_cmd <= $bits(out_cmd)'(CMD_GET_VALID);
delay_val <= 0;
waddr_end <= $bits(waddr)'(SIZE-1);
delay_cntr <= 0;
delta <= 0;
prev_trigger_id <= 0;
read_delta <= 0;
started <= 0;
delta_flush <= 0;
prev_trigger_id <= 0;
read_offset <= 0;
read_delta <= 0;
data_valid <= 0;
end else begin
if (bus_write) begin
@@ -88,12 +88,12 @@ module VX_scope #(
end
if (start && !started) begin
started <= 1;
started <= 1;
delta_flush <= 1;
if (0 == delay_val) begin
start_wait <= 0;
recording <= 1;
delay_cntr <= 0;
delta_flush <= 1;
delay_cntr <= 0;
end else begin
start_wait <= 1;
recording <= 0;
@@ -104,9 +104,8 @@ module VX_scope #(
if (start_wait) begin
delay_cntr <= delay_cntr - 1;
if (1 == delay_cntr) begin
start_wait <= 0;
recording <= 1;
delta_flush <= 1;
start_wait <= 0;
recording <= 1;
end
end
@@ -181,7 +180,7 @@ module VX_scope #(
`ifdef DBG_PRINT_SCOPE
always @(posedge clk) begin
if (bus_read) begin
$display("%t: scope-read: cmd=%0d, out=0x%0h, addr=%0d", $time, out_cmd, bus_out, raddr);
$display("%t: scope-read: cmd=%0d, out=%0h, addr=%0d", $time, out_cmd, bus_out, raddr);
end
if (bus_write) begin
$display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data);